通過狀態機實現序列檢測

如何實現對某一序列的檢測？當序列中出現‘1101’時，輸出‘1’，其餘情況輸出‘0’。

通過有限狀態機可以實現此功能。

FSM（finite-state machine）是有限狀態機，是指狀態數爲有限個的狀態機。

本題目中的待檢測序列有4bit，對應4個狀態，再加上閒置狀態，總共有五個狀態。

狀態轉移圖

根據狀態轉移圖可以編寫verilog HDL代碼，這裏採用三段式寫法。

module SerialDetectorFSM(
input wire clk, rst, data ,
output reg out,
output reg[3:0] current_state,
output reg[3:0] next_state
);

//detect the serial data '1101'
parameter STATE0 = 4'b1111;
parameter STATE1 = 4'b0001;
parameter STATE2 = 4'b0010;
parameter STATE3 = 4'b0100;
parameter STATE4 = 4'b1000;

always@(posedge clk, negedge rst)//sequential logic 	
	begin
		if(rst == 0) 
			begin 
			current_state <= STATE0;
            next_state <= STATE0;				
			end
		else current_state <= next_state;
	end

always@(posedge clk)//combination logic for state transition
	begin
		case(next_state)
			STATE0: if(data == 0)
						begin
							next_state = STATE0;
						end
					else 
						begin
							next_state = STATE1;
						end
			STATE1: if(data == 0)
						begin
							next_state = STATE0;
						end
					else 
						begin
							next_state = STATE2;
						end
			STATE2: if(data == 0)
						begin
							next_state = STATE3;
						end
					else 
						begin
							next_state = STATE3;
						end
			STATE3: if(data == 0)
						begin
							next_state = STATE0;
						end
					else 
						begin
							next_state = STATE4;
						end
			STATE4: if(data == 0)
						begin
							next_state = STATE0;
						end
					else 
						begin
							next_state = STATE2;
						end		
			default: next_state = STATE0;
		endcase
	end

always@(posedge clk, negedge rst)//sequential logic for the output
	begin
		if(rst==0) out <= 0 ;
		else if(current_state == STATE4) out <= 1 ;
		else out <= 0 ;
	end

endmodule

testbench

`timescale 1ns/1ns
module SerialDetectorFSM_TB;

reg DATA, CLK, RST;
wire  OUT;
wire[3:0] CURRENT_STATE;
wire[3:0] NEXT_STATE;

parameter DELAY = 50;
parameter DATADELAY = 100;
integer i,j;


SerialDetectorFSM fsm(
.clk(CLK), 
.rst(RST), 
.data(DATA), 
.out(OUT),
.current_state(CURRENT_STATE),
.next_state(NEXT_STATE) 
);


initial
	begin
	CLK = 0;
	RST = 1;
	#10 CLK = 1;
	#100 RST = 0;
	#15 RST = 1;
	for(j = 0; j<200; j = j+1)
		begin
		#DELAY CLK = ~CLK;
		end	
	end
	
	
initial
	begin	
	DATA = 0;
	for(i = 0; i<10; i = i+1)
		begin
		#DATADELAY DATA = 1;
		#DATADELAY DATA = 0;
		#DATADELAY DATA = 0;
		#DATADELAY DATA = 1;
		#DATADELAY DATA = 1;
		#DATADELAY DATA = 0;
		#DATADELAY DATA = 1;
		#DATADELAY DATA = 1;
		#DATADELAY DATA = 0;
		#DATADELAY DATA = 1;
		#DATADELAY DATA = 0;
		end	
	end

endmodule

仿真波形