如何实现对某一序列的检测?当序列中出现‘1101’时,输出‘1’,其余情况输出‘0’。
通过有限状态机可以实现此功能。
FSM(finite-state machine)是有限状态机,是指状态数为有限个的状态机。
本题目中的待检测序列有4bit,对应4个状态,再加上闲置状态,总共有五个状态。
状态转移图
根据状态转移图可以编写verilog HDL代码,这里采用三段式写法。
module SerialDetectorFSM(
input wire clk, rst, data ,
output reg out,
output reg[3:0] current_state,
output reg[3:0] next_state
);
//detect the serial data '1101'
parameter STATE0 = 4'b1111;
parameter STATE1 = 4'b0001;
parameter STATE2 = 4'b0010;
parameter STATE3 = 4'b0100;
parameter STATE4 = 4'b1000;
always@(posedge clk, negedge rst)//sequential logic
begin
if(rst == 0)
begin
current_state <= STATE0;
next_state <= STATE0;
end
else current_state <= next_state;
end
always@(posedge clk)//combination logic for state transition
begin
case(next_state)
STATE0: if(data == 0)
begin
next_state = STATE0;
end
else
begin
next_state = STATE1;
end
STATE1: if(data == 0)
begin
next_state = STATE0;
end
else
begin
next_state = STATE2;
end
STATE2: if(data == 0)
begin
next_state = STATE3;
end
else
begin
next_state = STATE3;
end
STATE3: if(data == 0)
begin
next_state = STATE0;
end
else
begin
next_state = STATE4;
end
STATE4: if(data == 0)
begin
next_state = STATE0;
end
else
begin
next_state = STATE2;
end
default: next_state = STATE0;
endcase
end
always@(posedge clk, negedge rst)//sequential logic for the output
begin
if(rst==0) out <= 0 ;
else if(current_state == STATE4) out <= 1 ;
else out <= 0 ;
end
endmodule
testbench
`timescale 1ns/1ns
module SerialDetectorFSM_TB;
reg DATA, CLK, RST;
wire OUT;
wire[3:0] CURRENT_STATE;
wire[3:0] NEXT_STATE;
parameter DELAY = 50;
parameter DATADELAY = 100;
integer i,j;
SerialDetectorFSM fsm(
.clk(CLK),
.rst(RST),
.data(DATA),
.out(OUT),
.current_state(CURRENT_STATE),
.next_state(NEXT_STATE)
);
initial
begin
CLK = 0;
RST = 1;
#10 CLK = 1;
#100 RST = 0;
#15 RST = 1;
for(j = 0; j<200; j = j+1)
begin
#DELAY CLK = ~CLK;
end
end
initial
begin
DATA = 0;
for(i = 0; i<10; i = i+1)
begin
#DATADELAY DATA = 1;
#DATADELAY DATA = 0;
#DATADELAY DATA = 0;
#DATADELAY DATA = 1;
#DATADELAY DATA = 1;
#DATADELAY DATA = 0;
#DATADELAY DATA = 1;
#DATADELAY DATA = 1;
#DATADELAY DATA = 0;
#DATADELAY DATA = 1;
#DATADELAY DATA = 0;
end
end
endmodule
仿真波形