key words: critical path , cycles to access cache
In the pipeline shown, the address decoders of the arrays and the data aligner have been removed from the critical path by placing them in different cycles.
There are two critical paths in Figure 2.2. The one is the path that goes through the tag array, the tag comparison
and the way multiplexor control. The other is the one that goes through the data array and the way multiplexor data path.
and the way multiplexor control. The other is the one that goes through the data array and the way multiplexor data path.
the ways of the data array can share the same wires to the aligner. Another benefit of this design is that it has lower energy consumption: the way-enable signal only activates the way where the requested data resides.
. By removing the way multiplexor, we have relaxed the critical paths signifi-cantly. First, the data array to way multiplexor data path is entirely removed. Second, the length of the critical path through the tag array is reduced. This allows this design
to run at a higher frequency than the previous one. On the other hand, this design requires one more cycle to access the cache.