引言

本文在上一講逐漸熟悉了VCS的開關選項後，下面繼續介紹VCS的使用，我始終關注於熟悉工具的使用，在本系列中，對Verilog的語法不作深入研究，這樣可以加快前進的步伐。也爲了加快從FPGA中轉變到IC領域來。在本文中將介紹VCS 調試基礎。

1、基礎理論講義

—Afer completing this unit ,you should be able to:

Describe three methods of debugging Verilog code using VCS
Invoke UCLI debugger
Debug Verilog designs using UCLI

–VCS Debugging Suport
4. Trance and locate causes of errors
5. Three general debugging methods:

Verilog SystemVerilog System Task calls
VCS UCLI
VCS DVE(GUI)
Four factors to consider:
simulation speed
signal visibility
sgnal tractability
usability

Verilog System Task For Debugging 利用verilog的系統函數

Debug visibility:

$ display prints formatted message to console
$ strobe Like$dispaly except printing is delayed until all events in the current time step have executed
$ monitor Monitor signals listed and prints formatted message whenever one of the listed signals changes
$ time returns current simulation time as a 64bits integer

Stopping simulations:
$stop halts simulation lie a breakpoint
$finish halts simulation and terminated the simulation session
Simulation stimulus and reference:

$readmemh Reads ASCII data from a disk file,each digit is hexadecimal -$ readmemb
Reads ASCII dataform a disk file ,Each digit is binary

Debugging via UCLI(no-recom)不推薦使用UCLI方式來查看波形

Simulation speed
Speed depends on the scale of visibility you specify
Signal Vsisibiility
Signal Traceability
-Usability

Compile and Invoke UCLI Debugger

-Compile and invoke UCLI in one step(一步走，編譯並且調用UCLI)

$ vcs source.v -debug|debug_all -R -ucli
-ucli invokes UCLI and stop simulation time at time 0

-Compile and invoke UCLI in two step(分兩步走，先編譯，後執行可執行文件)
vcs source.v -debug|debug_all|debug_pp(debug_pp只打開部分調試開關，加快編譯速度)
invoke UCLI and stop simulation time at time 0
$simv -ucli

UCLI Debugger Command Line Option

-debug
enables command line debugging option. This flag does not enable line stepping.

-debug_all
enables command line debugging option including line stepping

-ucli
forces runtime to go into UCI mode by default

-gui
compile time option invokes the DVE gui when issured at run time

-l log_filename
captures simulation output ,such as user input UCLI commands and responses to UCLI commands.

-i input_filename
reads interactive UCLI commands from a file the switches readding from standard command line input

-k key_filename
writes interactive commands entered to input_filename,which can be used by a latter simv as -i input_filename
由於UCLI的陳舊，這裏不再強調。

退出UCLI
quit 即可

Problems in simulation?
if you suspect simlation is having problems

Determine whether or not time is advancing:
halt simulation by hiting ctrl+c 通過ctrl+c來退出仿真

check simulation time

continue simulation by typing in run at UCLI prompt
halt simulation again after a shor period of time

if simulation time has not changed,simulation may be caught in infinite loop or waiting for a phantom triger

-Determine potential location of problem:
Re-compile with -debug_all compile-time option
halt simulation
use UCLI command show to dispaly variables
trace code execution with UCLI command next

官方的文檔位置：

DVE（Discovery Visual Environment）
An intuitive and easy to use GUI
Quiickly fine bugs
RTL or Gates
Assertions
Testbench
Supports
Interactive
Post-simulaton analisis
Multiple languages
verilog
VHDL
SV
C++、C
NTB

波性文件vpd
verdi裏面的波性文件爲fsdb