一位前ARM工程师对RISC-V的批评

{"type":"doc","content":[{"type":"blockquote","content":[{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"本文最初完成于几年之前，彼时作者正在 ARM 公司担任执行核心验证工程师职位。"},{"type":"text","marks":[{"type":"strong"}],"text":"作者当时的工作深入或围绕多种处理器核心，而文中提到的观点深受这些经验的影响，换句话说，这些观点存在不同程度的偏见"},{"type":"text","text":"。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"作者依旧坚持认为 RISC-V 的设计并不完美，但同时也承认，如果现在需要搭建一个 32 或 64 位的 CPU，他在实现构建时也会从现有工具中受益。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"本文主要基于 RISC-V ISA 规范 v2.0，部分已更新至 v2.2。"}]}]},{"type":"heading","attrs":{"align":null,"level":2},"content":[{"type":"text","text":"原文前言：一些观点"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"RISC-V ISA 对极简主义的追求钻了牛角尖，它极力强调减少指令数量，规范编码等等。而这种追求则导致了错误的正交性（分支、调用、返回时重复使用同一指令），以及对赘余指令的需求，这些在程序大小和指令数量上都会影响到代码密度。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"以下面的 C 代码为例："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"int readidx(int *p, size_t idx){ return p[idx]; }\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"简单的数组索引，非常常见的操作。将其在 x86_64 中编译："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"mov eax, [rdi+rsi*4]ret\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"或者是 ARM 中："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"ldr r0, [r0, r1, lsl #2]bx lr \/\/ return\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"但是在 RISC-V 中需要的代码则是："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"# 很抱歉如果有任何语法错误，risc-v 并没有在线编译器slli a1, a1, 2add a0, a1, a1lw a0, a0, 0jalr r0, r1, 0 \/\/ return\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"RISC-V 的极简主义让解码器（CPU 前端）变得更简单，代价则是需要执行更多的指令。然而，相对于拓宽流水线这个难题而言，解码不规则指令的问题很好解决，主要难点在于确定指令的长度是否一致。x86 的众多前缀就是个极佳的反面教材。对指令集的简化不应追求极限。寄存器 + 移位寄存器的内存操作指令是程序中非常常见且简单的操作，对于 CPU 而言也很容易实现。即使无法直接执行，CPU 也可以相对轻松地将其分步执行，其操作复杂程度远逊色于融合简单操作的序列。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}}]}