[Synth 8-9486] formal port 'addr' has no actual or default value [D:/FPGA/TEST_CARD_HIT/top.vhd:492]
有端口沒有連接，在top文件中把端口加上
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: lvds3/u1/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/bindec_a.bindec_inst_a/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1.
新建ram的時候選擇global，不要選擇ooc（out of context）
內總線或者其他不需要對外映射管腳約束的，不要在top文件的entity top is ;port( ;中聲明爲in或者out，放在architecture RTL of top is中聲明爲signal rst: std_logic;就可以
entity top is
port(
sys_clk : in std_logic ;--需要管腳約束
);
end top;
architecture RTL of top is
signal lvds1_addr : std_logic_vector(11 downto 0);--不需要管腳約束
lvds1:lvds_interface port map
(
clk => sys_clk ,
addr => lvds1_addr
);
end rtl;