常見IC設計/FPGA面試問題之：FIFO深度計算

原文可以看FIFO Depth Calculation 這篇文章。

FIFO深度計算的關鍵在於：
在規定時間內傳輸的數據等於接收的數據，寫快讀慢的情況下，突發burst寫入的數據減去該burst時間內讀出的數據，多餘的數據需要能緩衝下來，讓接收端在剩下空閒的時間能從容地把多餘的數據讀出來。

下面看幾道例題。

case1：

• fA > fB with no idle cycles in both write and read.
• Writing frequency = fA = 80MHz.
• Reading Frequency = fB = 50MHz.
• Burst Length = No. of data items to be transferred = 120.
• There are no idle cycles in both reading and writing which means that, all the items in the burst will be written and read in consecutive clock cycles.

計算方法（本題假設寫數據和讀數據位寬相同）：

• 總傳輸數據爲120
• 把所有數據全部寫入FIFO需要時間爲120/80MHz=1500ns$120/80MHz=1500ns$
• 該時間段（1500ns）內可以從FIFO中讀出的數據爲1500ns∗50MHz=75$1500ns\ast 50MHz=75$
• 多餘的數據爲120−75=45$120-75=45$
• 所以FIFO的最小深度爲45

case2

• A > fB with one clk cycle delay between two successive reads and
  writes.

這種情況和case1相同

case3

• fA > fB with idle cycles in both write and read.
• Writing frequency = fA = 80MHz.
• Reading Frequency = fB = 50MHz.
• Burst Length = No. of data items to be transferred = 120.
• No. of idle cycles between two successive writes is = 1.
• No. of idle cycles between two successive reads is = 3.

計算方法

• 寫時鐘的等效頻率爲fW=fA/2=40MHz$fW=fA/2=40MHz$
• 讀時鐘的等效頻率爲fR=fB/4=12.5MHz$fR=fB/4=12.5MHz$
• 最小深度爲120−120/fW∗fR=83$120-120/fW\ast fR=83$

case4

• fA > fB with duty cycles given for wr_enb and rd_enb.
• Writing frequency = fA = 80MHz.
• Reading Frequency = fB = 50MHz.
• Burst Length = No. of data items to be transferred = 120.
• Duty cycle of wr_enb (write enable) = 50 % = ½.
• Duty cycle of wr_enb (write enable) = 25 % = ¼.

和case3相同，只是問題描述方式不同

case5

• fA < fB with no idle cycles in both write and read (i.e., the delay between two consecutive writes and reads is one clock cycle).
• Writing frequency = fA = 30MHz.
• Reading Frequency = fB = 50MHz.
• Burst Length = No. of data items to be transferred = 120.
• There are no idle cycles in both reading and writing which means that, all the items in the burst will be written and read in consecutive clock cycles.

這種寫慢讀快的情況fifo的深度爲1就夠了。

case6

• fA < fB with idle cycles in both write and read (duty cycles of wr_enb and rd_enb can also be given in these type of questions).
• Writing frequency = fA = 30MHz.
• Reading Frequency = fB = 50MHz.
• Burst Length = No. of data items to be transferred = 120.
• No. of idle cycles between two successive writes is = 1.
• No. of idle cycles between two successive reads is = 3.

這個case看似是寫慢讀快，但是因爲有idle週期的存在導致

• 寫時鐘的等效頻率爲fW=fA/2=15MHz$fW=fA/2=15MHz$
• 讀時鐘的等效頻率爲fR=fB/4=12.5MHz$fR=fB/4=12.5MHz$
• 最小深度爲120−120/fW∗fR=20$120-120/fW\ast fR=20$

case7

• fA = fB with no idle cycles in both write and read (i.e., the delay between two consecutive writes and reads is one clock cycle).
• Writing frequency = fA = fB = 30MHz.
• Burst Length = No. of data items to be transferred = 120.
• There are no idle cycles in both reading and writing which means that, all the items in the burst will be written and read in consecutive clock cycles.

這種情況不需要fifo，如果clka和clkb有相位差，可以採用兩級dff或者深度爲1的fifo即可。

case8

• fA = fB with idle cycles in both write and read (duty cycles of wr_enb and rd_enb can also be given in these type of questions).
• Writing frequency = fA = 50MHz.
• Reading Frequency = fB = 50MHz.
• Burst Length = No. of data items to be transferred = 120.
• No. of idle cycles between two successive writes is = 1.
• No. of idle cycles between two successive reads is = 3.

同樣算等效時鐘頻率就行了。

case9

• Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
• Outgoing Data= 8 DATA/10 Clock.
• Burst size = 160

可能有下面幾種情況，以及每種情況下寫完160個burst所需要的週期數

考慮最壞的情況case4，160個cycle就要寫完160個數據的burst，在這160個時鐘週期內能從fifo中讀走 160/10∗8=128$160/10\ast 8=128$ 個數據，所以fifo的深度爲160-128=32

case10

• Frequency (clk A) = frequency (clk B)/4
• Period (en_B) = period (clk_A)*100
• Duty cycle (en_B) = 25%

假設clkb=100MHz, 則clka=25MHz, 看起來是一個寫慢讀快的情況，不需要fifo。

但是因爲第三個條件en_B的duty cycle只有1/4個週期，也就是在這個burst期間只有1/4的時間能從fifo中讀出數據，這1/4週期的時間內是讀快寫慢，fifo不需要緩存數據。其餘3/4個週期只有寫，沒有讀，所以fifo的深度要能緩存下這3/4個週期中寫入的數據。

從第二個條件可以看出burst的數據爲100，總burst的時間爲 100/25MHz=4000ns$100/25MHz=4000ns$ , 3/4個週期就是3000ns，所以fifo的深度爲 3000ns∗25MHz=75$3000ns\ast 25MHz=75$