1.1 常用的時鐘結構
Three basic I/O architectures
• Common Clock (Synchronous)
• Forward Clock (Source Synchronous)
• Embedded Clock (Clock Recovery)
1.2 PCIE時鐘結構
1.2.1 CC mode(common Refclk Rx Architecture)
Most of the SSC jitter sourced by the Refclk is propagated equally through Tx and Rx PLLs, and so intrinsically tracks LF jitter. This is particularly true for SSC which tends to be low frequency.
因爲TJ中的低頻分量主要來自SSC，CC mode下在Rx看到的jitter經過H1(s)-H2(s)系統，低頻分量減小，導致LF jitter變小。
但這種好處的前提是Tx-Rx的delay不能過大，所以spec中規定Tx-Rx transport delay<12ns(only for CC mode)
1.2.2 IR mode
Separate Refclk Independent SSC (SRIS) Architecture
Separate Reference Clocks With No SSC (SRNS) Architecture
The maximum difference with SRNS is 600 ppm which can result in a clock shift once every 1666 clocks. The maximum difference with SRIS is 5600 ppm which can result in a clock shift every 178 clocks.
1.2.3 Refclk jitter computation
1.2.3.1 CC clock
Cc mode下需要計算兩個PLL 帶寬疊加起來的效果，PCIe spec中給出了不同的帶寬組合，下圖以pcie1.1爲例計算的jitter傳輸函數。
1.2.3.2 Data clock
1.2.3.3 SRNS
The PCIe standards do not specify jitter limits for this clock architecture, although it states that jitter must be considerably tighter than for the other two architectures
1.2.3.4 SRIS
This architecture now burdens the RX with tracking and rejecting the phase shift between the RX and TX that is inherent in the two independent refclks with SSC. The ability to support this architecture requires the CDR to have a second order high-pass filter in the transfer function in order to reject the phase shift that is inherent in the independent SSC implementation
