第一部分作業
總體思路:先設計一個合適頻率的時間基準模塊,用溢出信號作爲是使能信號輸入,再設計符合顯示要求的計數器,再設計數碼管顯示模塊,顯示出來。
人工繪製RTL圖:
計數部分
時間基準部分
quartus生成RTL結構圖
總體結構:
計數部分:
時間基準部分
數碼管顯示部分
SignalTap截圖
視頻鏈接:
代碼:
////////////////計數程序///////////////////////
module jishu(
CLK , // 時鐘
CNTVAL, // 輸出
rst , //復位
en ); //使能
input CLK,rst;
input en;
output [4-1:0] CNTVAL;
reg [4-1:0] max=6;//計數最大值
reg [4-1:0] CNTVAL;
always @ (posedge CLK or posedge rst ) begin
if(rst) begin //高電平復位
CNTVAL <= 0;
max<=6; //復位同時從計數最大值從6開始
end
else begin
if(en)begin //使能信號低電平有效,低電平時輸出值保持不變
if(CNTVAL >= max) begin //超出計數最大值,從零重新開始
CNTVAL <= 0;
if(max<9) //計數最大值從6開始遞增,直到9
max<=max+1'b1;
else
max<=6;
end
else
CNTVAL <= CNTVAL + 1'b1;
end
else CNTVAL <= CNTVAL ;
end
end
endmodule
////////////////數碼管顯示///////////////////////
module shumaguan (
bcd,
seg);
input [3:0]bcd;//實際輸出數值
output seg;
reg [7:0]seg; //各個引腳對應的高低電平
always @(bcd) begin
case (bcd)
4'b0000: seg = 8'h C0;
4'b0001: seg = 8'h F9; //1
4'b0010: seg = 8'h A4; //2
4'b0011: seg = 8'h B0; //3
4'b0100: seg = 8'h 99; //4
4'b0101: seg = 8'h 92; //5
4'b0110: seg = 8'h 82; //6
4'b0111: seg = 8'h F8; //7
4'b1000: seg = 8'h 80; //8
4'b1001: seg = 8'h 90; //9
endcase
end
endmodule
//////////////////// 時間基準模塊/////////////////////////
module cnt_sync(
CLK , // clock
CNTVAL, // counter value
OV ); // overflow
input CLK;
output [32-1:0] CNTVAL;
output OV;
parameter MAX_VAL = 25_000_000;//可以控制溢出信號的輸出頻率=50000000/MAX_VAL
reg [32-1:0] CNTVAL;
reg OV; //溢出信號作爲下一級的時鐘
always @ (posedge CLK) begin //計數器的功能
if(CNTVAL >= MAX_VAL)
CNTVAL <= 0;
else
CNTVAL <= CNTVAL + 1'b1;
end
always @ (CNTVAL) begin //計數計滿輸出一次溢出信號
if(CNTVAL == MAX_VAL)
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
第二部分作業
總體思路:
先設計一個合適頻率的時間基準模塊,用溢出信號作爲是使能信號輸入,再設計符合一個計數週期爲34的計數器(因爲數碼管顯示週期爲34),再設計數碼管顯示模塊,顯示出對應的結果。
人工繪製RTL圖:
計數部分
時間準基部分
quartus生成RTL結構圖
總體結構:
計數部分:
時間準基部分:
數碼管顯示部分:
1.最左邊的數碼管
2.左邊第二個數碼管
3.左邊第三個數碼管
4.最右邊的數碼管
SignalTap截圖
視頻鏈接:http://www.miaopai.com/show/7raWeMNB7vNCY6ebutoyVQ__.htm
module jishu0_34( rst , en , CLK , CNTVAL); input CLK,en,rst; output CNTVAL; reg [6-1:0] CNTVAL=0; always @ (posedge CLK or posedge rst ) begin if (rst) CNTVAL<=63; else begin if(en) begin if(CNTVAL <33) CNTVAL <= CNTVAL + 1'b1; else CNTVAL <= 0; end else CNTVAL <= CNTVAL; end end endmodule
///////////////////////////////////////////////
module cnt_sync(
CLK , // 時鐘
CNTVAL, // 輸出
OV ); // 溢出信號
input CLK;
output [32-1:0] CNTVAL;
output OV;
parameter MAX_VAL = 50_000_000;
reg [32-1:0] CNTVAL;
reg OV; //溢出信號作爲下一級的使能
always @ (posedge CLK) begin //計數器的功能
if(CNTVAL >= MAX_VAL)
CNTVAL <= 0;
else
CNTVAL <= CNTVAL + 1'b1;
end
always @ (CNTVAL) begin //計數計滿輸出一次溢出信號
if(CNTVAL == MAX_VAL)
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
/////////////////////////////////////////////////////////
module shumaguan9 (
bcd,
seg);
input [5:0]bcd;//實際計數數值
output seg;
reg [7:0]seg; //各個引腳對應的高低電平
always @(bcd) begin // 計數到24時數碼管顯示0到9,否則數碼管不亮
case (bcd)
6'b011000: seg = 8'h C0; //0
6'b011001: seg = 8'h F9; //1
6'b011010: seg = 8'h A4; //2
6'b011011: seg = 8'h B0; //3
6'b011100: seg = 8'h 99; //4
6'b011101: seg = 8'h 92; //5
6'b011110: seg = 8'h 82; //6
6'b011111: seg = 8'h F8; //7
6'b100000: seg = 8'h 80; //8
6'b100001: seg = 8'h 90; //9
6'b100010: seg = 8'h FF;
default seg = 8'h FF;
endcase
end
endmodule
/////////////////////////////////////////////////////
module shumaguan8 (
bcd,
seg);
input [5:0]bcd;//實際計數數值
output seg;
reg [7:0]seg; //各個引腳對應的高低電平
always @(bcd) begin //計數值爲15時數碼管顯示0到8,否則數碼管不亮
case (bcd)
6'b001111: seg = 8'h C0; //0
6'b010000: seg = 8'h F9; //1
6'b010001: seg = 8'h A4; //2
6'b010010: seg = 8'h B0; //3
6'b010011: seg = 8'h 99; //4
6'b010100: seg = 8'h 92; //5
6'b010101: seg = 8'h 82; //6
6'b010110: seg = 8'h F8; //7
6'b010111: seg = 8'h 80; //8
default seg = 8'h FF;
endcase
end
endmodule
module shumaguan7 (
bcd,
seg);
input [5:0]bcd;//實際計數數值
output seg;
reg [7:0]seg; //各個引腳對應的高低電平
always @(bcd) begin //計數值爲7時數碼管顯示0到7,否則數碼管不亮
case (bcd)
6'b000111: seg = 8'h C0; //0
6'b001000: seg = 8'h F9; //1
6'b001001: seg = 8'h A4; //2
6'b001010: seg = 8'h B0; //3
6'b001011: seg = 8'h 99; //4
6'b001100: seg = 8'h 92; //5
6'b001101: seg = 8'h 82; //6
6'b001110: seg = 8'h F8; //7
default seg = 8'h FF;
endcase
end
endmodule
module shumaguan6(
bcd,
seg);
input [5:0]bcd;//實際計數數值
output seg;
reg [7:0]seg; //各個引腳對應的高低電平
always @(bcd) begin // 計數值爲0時數碼管顯示0到6,否則數碼管不亮
case (bcd)
6'b000000: seg = 8'h C0;//0
6'b000001: seg = 8'h F9;//1
6'b000010: seg = 8'h A4;//2
6'b000011: seg = 8'h B0;//3
6'b000100: seg = 8'h 99;//4
6'b000101: seg = 8'h 92;//5
6'b000110: seg = 8'h 82;//6
default seg = 8'h FF;
endcase
end
endmodule