很簡單的例子，僅僅加時鐘週期約束的條件下時序波形圖分析

爲什麼建立時間的datarequiretime  會在lauch clock的後面 是因爲launch clock到目的寄存器還有一段延遲

簡單的例子，僅僅加時鐘週期約束的條件下，

 

create_clock -period 10.000 -name clk_in [get_ports {clk_in}]

 

 

用TimeQuest分析僅會得到一路path的分析，reg1 to reg2，時序圖如下：

clock arrival time=latch edge+clock network delay to destination register                                           

11.110=10+1.110

data required time =clock arrival time -u/tsu                                                                                   

11.125=11.110-(-0.015)

data arrival time=launch edge +clock network delay source register +u/tco+register-to-register delay  

1.438=0+1.148+0.199+0.091

clock setup slack =data required time -data arrival time                                                                   

9.687 = 11.125-1.438

 

set_input_delay -clock { clk_in } -add_delay 1.200 [get_ports {data_in}] set_output_delay -clock { clk_in } -add_delay 2.000 [get_ports data_out]

重新運行TimeQuest，可以看到3個path分析

　　1) data_in to reg1

 

2) reg1 to reg2

 

3) reg2 to data_out

 　可以看到，輸入路徑在data arrival time上加上了input delay；輸出路徑在data required time上減去了output delay;分別表現爲對setup和hold時間的影響。