1、配置DDS的IP
設置輸出位寬和相位位寬,時鐘設置爲100MHz。
設置爲stream
默認
2、添加仿真tb
`timescale 1ns / 100ps
module AA_tb(
);
reg clk;
reg rst_n;
initial
begin
#0 clk = 1'b0;
#2 rst_n = 1'b0;
#200 rst_n = 1'b1;
end
always #5 clk = ~clk;
wire [15:0] data1_i,data1_q;
wire data1_valid;
top top(
.clk(clk),
.ad_data(),
.data1_i(data1_i),
.data1_q(data1_q),
.data1_valid(data1_valid)
);
integer w_file;
initial w_file = $fopen("F:\data_i.txt");
integer w_file2;
initial w_file2 = $fopen("F:\data_q.txt");
reg [15:0] i =0;
always @ (posedge clk)
begin
if (!rst_n)
i <=0;
else if(data1_valid==1)
if(i<1024)
begin
i <=i+1;
$fdisplay(w_file,"%d",data1_i);
$fdisplay(w_file2,"%d",data1_q);
end
else
begin
$fclose(w_file);
$fclose(w_file2);
end
end
endmodule
頂層文件
module top(
input clk, //90MHz
input [15:0] ad_data,
output [15:0] data1_i, //240k
output [15:0] data1_q,
output data1_valid
);
wire sys_clk,sys_clkx2;
wire locked,rst_n;
sys_mmcm_clk sys_clk_gen
(
.clk_in1(clk),
.clk_out1(sys_clk),
.reset(1'b0),
.locked(locked)
);
reset_gen reset_gen
(
.aclk(sys_clk),
.aclk_locked(locked),
.I_soft_resetn(locked),
.aresetn(rst_n)
);
wire [15:0] a_sin,a_cos;
wire m_axis_data_tvalid;
wire [31:0] m_axis_data_tdata;
assign a_sin = m_axis_data_tdata[31:16]+32768;
assign a_cos = m_axis_data_tdata[15:0]+32768;
assign data1_i = a_sin;
assign data1_q = a_cos;
assign data1_valid = m_axis_data_tvalid;
dds_compiler_41m4 u_dds_compiler_41m4
(
.aclk (sys_clk) ,
.s_axis_phase_tvalid(rst_n),
.s_axis_phase_tdata (32'd536870912),
.m_axis_data_tvalid (m_axis_data_tvalid),
.m_axis_data_tdata (m_axis_data_tdata)
);
endmodule
3、matlab導入數據驗證
matlab的代碼:
clear;close all;
fs=100e6 ;
N=1024;
n= 0:N-1;
f=n*fs/N;
XREAL = importdata('data_q.txt');
XIMAG = importdata('data_i.txt');
XREAL22 = XREAL -32768;
XIMAG22 = XIMAG-32768;
%虛部
Y = XIMAG22;
fftxx=fft(Y,N);
mag = abs(fftxx);
figure(1),
plot(f,mag);
%實部
Y2 = XREAL22;
fftxx2=fft(Y2,N);
mag2 = abs(fftxx2);
figure(2),
plot(f,mag2);
%IQ信號
Y3 =XREAL22 +XIMAG22*1i;
fftxx3=fft(Y3,N);
mag3 = abs((fftxx3));
figure(3),
plot(f,mag3);