SGX 名稱字典

• 1. SGX
     Intel Software Guard Extensions.

• GPRs
  General purpose registers.

• 64-bit integers / pointers

RAX	RBX	RCX	RDX
RSI	RDI	RBP	RSP
R8	R9	R10	R11
R12	R13	R14	R15

64-bit special-purse registers

RIP - instruction pointer

RSP - stack pointer

RFLAGS - status / control bits

• ignored segment registers

CS	code segment
DS	data segment
ES	extra segment determined by the programmer
SS	stack segment

• segment registers

FS	64-bit FS base
GS	64-bit GS base

FS and GX registers store segments covering thread-local-storage.
The registers FS and GS are segment registers. They have no processor-defined purpose, but instead are given purpose by the OS’s running them. In Windows 64-bit the GS register is used to point to operating system defined structures. FS and GS are commonly used by OS kernels to access thread-specific memory. In windows, the GS register is used to manage thread-specific memory. The linux kernel uses GS to access cpu-specific memory

• RFLAGS register
  RFLAGS are individually used to store comparison results and control various instructions.
  Software may use other registers to interact with specific processor features, some of which are show in Table 2.1.
  Table 2.1: Sample feature-specific Intel architecture registers.

Feature	Registers	XCR0 bit
FPU	FP0 - FP7, FSW, FTW	0
SSE	MM0 - MM7, XMM0 - XMM15, XMCSR	1
AVX	YMM0 - YMM15	2
MPX	BND0 - BND 3	3
MPX	BNDCFGU, BNDSTATUS	4
AVX-512	K0 - K7	5
AVX-512	ZMM0_H - ZMM15_H	6
AVX-512	ZMM16 - ZMM31	7
PK	PKRU	9

• RFBM
  requested-feature bitmap: The XSAVE instruction takes in a RFBM, and writes the registers used by the features whose RFBM bits are set to 1 in a memory.

• RPL
  Requested privilege level (rings 0 and 3)

• TLS
  Thread Local Storage.

• GDT 2.7
  Global Descriptor Table

• TR 2.7
  Task Register

• TSS 2.7
  Task State Segment

• IST 2.7
  Interrupt Stack Table

• 2. PRM 5.1
     Processor Reserved Memory(PRM), which is a submit of DRAM that cannot be directly accessed by other software, including system software and SMM code.
• 3. SMM
     System Management Mode (SMM, sometimes called ring -2 in reference to protection rings) is an operating mode of x86 central processor units (CPUs) in which all normal execution, including the operating system, is suspended. An alternate software system which usually resides in the computer’s firmware, or a hardware-assisted debugger, is then executed with high privileges.
• 4. SDM 5
     Intel’s Software Developer Manual
• 5. PRMRR 5.1
     Processor Reserved Memory(PRM) range registers.
• 6. EPC 5.1
     The Enclave Page Cache, which is a submit of the PRM.

• The Enclave Page Cache Map(EPCM)
  The EPCM is an array with one entry per EPC page, so computing the address of a page’s EPCM only requires a bitwise shift operation and an addition.

• PT 5.1
  page type

• PT_REG
  Regular type of PT, this page store an enclave’s code and data.

• PT_SECS
  SECS: The SGX Enclave Control Structures. An enclave’s identity is almost synonymous to its SECS. SDM states that each enclave’s measurement is stored in its SECS.

• ELRANGE
  The Enclave Linear Address Range, which is used to map the code and the sensitive data stored in the enclave’s EPC pages. ELRANGE is specified using (the BASEADDR field) and a size (the SIZE) in the enclave’s SECS.

• SGX Enclave Attributes
  The execution environment of an enclave is heavily influenced by the value of the ATTRIBUTES fields in the enclaves’s SECS.

Field	Bits	Description
DEBUG	1	Opts into enclave debugging features.
XFRM	64	The value of XCR0 (a register in CPU) while this enclave’s code is executed.