BRAM(Block RAM)是FPGA中重要资源,具体什么请百度。今天在把玩一个ice51(https://github.com/ashleyjr/ice51.git)开源IP时,发现了这个好东西,权当兴趣爱好!
顺便研究了下综合工具:yosys(https://github.com/YosysHQ/yosys.git)、arachne-pnr(https://github.com/YosysHQ/arachne-pnr.git)、
icestorm(https://github.com/cliffordwolf/icestorm.git)
总之,转来转去,我就到了icestorm/icebram
那就来研究一下,顺便也学习下更多的VDHL、Verilog语法。
该例子中生成的verilog如下:
demo.v
// bram_width = 20
// bram_depth = 768
// numrports = 1
module demo (
input [9:0] raddr0,
output reg [19:0] rdata0,
input [9:0] waddr,
input [19:0] wdata,
input wen, clk
);
reg [19:0] memory [0:767];
initial $readmemh("demo_dat0.hex", memory);
always @(posedge clk) rdata0 <= memory[raddr0];
always @(posedge clk) if (wen) memory[waddr] <= wdata;
endmodule
demo_tb.v
module demo_tb;
reg clk = 0;
always #5 clk = ~clk;
integer i, errcnt = 0;
reg [9:0] addr;
wire [19:0] rdata0;
reg [19:0] refmem [0:767];
initial $readmemh("demo_dat1.hex", refmem);
demo uut (
.raddr0(addr+10'd0),
.rdata0(rdata0),
.wen(1'b0),
.clk(clk)
);
initial begin
$dumpfile ("demo_tb.vcd");
$dumpvars(-1, demo_tb);
repeat (10) @(negedge clk);
for (i = 0; i < 768; i = i + 1) begin
addr <= i;
@(posedge clk);
@(negedge clk);
if (i+0 < 768 && refmem[i+0] !== rdata0) begin errcnt = errcnt+1; $display("ERROR @%x: %05x != %05x", i+0, refmem[i+0], rdata0); end
end
if (errcnt == 0)
$display("All tests OK.");
else
$display("Found %1d ERROR(s).", errcnt);
$finish;
end
endmodule
1、目录结构
编译好里面的工具,运行rundemo.sh(环境MingW32)
2、所需依赖
3、数据准备好了,就可以运行查看结果了: