quartus Ⅱ 12.1 使用教程（2） modelsim 仿真

鑑於每次modelsim時間長了不用就忘記怎麼使用，所以這裏就直接寫一篇，以後忘記了直接來看這個使用教程

所要仿真的工程只是一個簡單的頻率輸出工程，將輸入的50M時鐘計數100次翻轉一次，然後輸出這個時鐘

原工程程序

module clk_out_test(
	i_clk,
	i_rst_n,
	clk_out

);

input		i_clk;
input		i_rst_n;
output	clk_out;

reg	[6:0] count;
reg			clk_out_reg;


always@(posedge i_clk or negedge i_rst_n)begin
		if(i_rst_n == 1'b0)
				count	<=	7'd0;
		else	if(count	==	7'd99)
				count	<=	7'd0;
		else
				count	<=	count	+ 1'b1;
end

always@(posedge i_clk or negedge i_rst_n)begin
		if(i_rst_n == 1'b0)
				clk_out_reg	<=	1'd0;
		else	if(count	==	7'd99)
				clk_out_reg	<=	~clk_out_reg;
		else
				clk_out_reg	<=	clk_out_reg;
end

assign	clk_out	=	clk_out_reg;

endmodule

仿真激勵文件

// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "08/04/2019 18:04:20"
                                                                                
// Verilog Test Bench template for design : clk_out_test
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ps/ 1 ps
module clk_out_test_vlg_tst();
// constants                                           
// general purpose registers
// test vector input registers
reg i_clk;
reg i_rst_n;
// wires                                               
wire clk_out;

// assign statements (if any)                          
clk_out_test i1 (
// port map - connection between master ports and signals/registers   
	.clk_out(clk_out),
	.i_clk(i_clk),
	.i_rst_n(i_rst_n)
);
initial                                                
begin                                                  
i_clk = 0;
i_rst_n = 0;
#100
i_rst_n = 1'b1;
                                                                
end                                                    
always #10 i_clk = ~i_clk;                                               
                                                    
endmodule

打開modelsim