FPGA驱动LCD显示中文字符“年”程序
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_driver is
Port ( clk: in std_logic;--状态机时钟信号，同时也是液晶时钟信号，其周期应该满足液晶数据的建立时间
reset : in std_logic;
lcdda : out std_logic;--寄存器选择信号
lcdrw : out std_logic;--液晶读写信号
lcden : out std_logic;--液晶时钟信号
data : out std_logic_vector(7 downto 0));--液晶数据信号
end lcd_driver;
architecture Behavioral of lcd_driver is
type state is (set_dlnf,set_cursor,set_dcb,set _cgram,write _cgram,set_ddram,write_data); --定义状态
signal current_state:state;
type ram2 is array(0 to 7) of std_logic_vector(7 downto 0);constant cgram:ram2:=(("00001000"),("00001111"),("00010010"),
("00001111"),("00001010"),("00011111"),("00000010"),("00000010"));--年字符数据存储器
signal clk : std_logic;
begin
lcden <= clk ; --液晶时钟信号
lcdrw <= '0' ; --写数据
control:process(clk,reset,current_state) --液晶驱动控制器
variable cnt1: std_logic_vector(2 downto 0); --定义变量cnt1
begin
if reset='0'then
current_state<=set_dlnf;
cnt1:=(others => '1');--将其所有位都赋为1
lcdda<='0';
elsif rising_edge(clk)then
current_state <= current_state ;
lcdda <= '0';
case current_state is
when set_dlnf=>
data<="00111100";--3cH
current_state<=set_cursor;
when set_cursor=>
data<="00000110";--06H
current_state<=set_dcb;
when set_dcb=>
data<="00001111";--0fH
current_state<=set_ cgram;
when set_ cgram=>
data<="01000000";--40H
current_state<=write_ cgram;
when write_ cgram=> --向CGRAM中写入“年”
lcdda<='1';
cnt1:=cnt1+1;
data<=cgram(conv_integer(cnt1));
if cnt1 = "111" then
current_state<=set_ddram;
end if;
when set_ddram=>--从第一行的起始地址开始显示
data<="10000000";--80H
current_state<=write_data;
when write_data=>
lcdda<='1';
data<="00000000"; --写入字符“年”
when others => null;
end case;
end if;
end process;
end Behavioral;
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