Overview
The STM32 timer peripherals can be clocked by an external source clock, but it does not mean that the APB (advanced peripheral bus) clock is not required. An STM32 timer peripheral synchronizes the external clock signal with its own core clock (which is the APB clock). The resulting synchronized clock signal is fed into the timer’s prescaler which by turn feeds the timer’s counter.
An STM32 timer peripheral requires two clock sources to keep updating its time base continuously (see Figure 7). The external clock-source period is the time unit used to update the timer peripherals’ time base.
STM32的外部時鐘源的使用需要APB高級分離總線的時鐘支持
There are two ways to synchronize (or externally clock) an STM32 timer:
• External source clock mode 1: by feeding the external clock signal into one of the timer channel inputs, TIx inputs.
時鐘通道會接入Master、Slave控制模塊，所以，可以接入時鐘通道
• External source clock mode 2: by feeding the external clock signal into the timer ETR input (if it is implemented and available).
也可以通過ETR INPUT直接接入Master、Slave控制模塊
The Figure 8 below shows the clock path for both external clock-source modes.
Synchronization block
Before introducing the modes of timer peripheral clocking by an external clock-source, it is important to first introduce the synchronization mechanism implemented by the STM32 timer peripherals when dealing with external signals. External signals are the signals coming from outside of the timer peripheral. They might be synchronized with a clock signal different from the one used by the timer peripheral or they might be fully asynchronous. A timer peripheral needs to deal with and handle external signals that may be fully asynchronous and adjust its outputs state or waveform accordingly. A timer peripheral also needs to be able to inform the software about the timestamp on which a signal on a given timer input changed its state (for example a signal toggling).
To deal with a fully asynchronous signal, a timer peripheral needs first to resynchronize it with its own clock signal. It might need to esynchronize for example with the timer core logic clock signal before feeding the resulting signal to the different sub-blocs of the timer peripheral. This action protects the timer core logic from going into metastability issues. Figure 9 shows the synoptic diagram for the synchronization circuit used to synchronize external signals fed into the timer inputs. The synchronization circuit is mainly composed of two cascaded D flip-flops that are clocked by the timer core clock signal. The external signal is fed into the first stage D flip-flop input where the synchronized signal is retrieved from the output of the second D flip-flop. This synchronization circuit introduces a delay of at least two timer core clock cycles and at most three clock cycles. The timer embeds “synch first” on all inputs except on the ETR where there is a prescaler first then re-synch.
通過串聯的兩個D觸發器，將ETR和APB的CLK通過延遲的方式同步起來，其中APB的時鐘必須是ETR的3倍以上，該同步才能完成。
The external clock-source mode 1
When the external clock-source mode 1 is activated, any signal that can be routed into the TRGI internal timer signal can as well clock the timer counter. Figure 8 shows the possible
所有能夠接入到TRGI的信號，都可以作爲定時器的計數時鐘
clock source for the timer counter, which are:
• The ETRF input signal: ETR signal after being prescaled, synchronized then filtered.外部信號，可變分頻、同步、過濾
• The inter-timer peripherals synchronization signals (ITR inputs)內部定時器同步
• The TI1FD signal which is the output of timer channel1 but which sensitive to both signal edges (each transition of the timer input 1 generates a pulse)
• The TI1FP1 (TI1FP1:Timer Input 1 Filtered Priority channel 1)and TI2FP2 input signals that are the synchronized, filtered then the TI1 and TI2 prescaled timer inputs, respectively.(本節詳細解釋）
This section deals only with the external clock mode 1 when an external source clock is fed into the timer through one of its inputs, in other words when a clock is fed into the timer through the ETR, TI1 or TI2 timer inputs.
Using the ETR input for feeding the timer is an alternative configuration for the external clock-source mode 2, so it is not detailed further within this section. The corresponding reference manual contains the right configuration to activate this clocking alternative.
Timer inputs, TI1 and TI2 as clock source
Only TI1 and TI2 inputs can be used to feed a clock signal into the timer counter when the external clock mode 1 is activated. If the timer does already embed four channels, the TI3 and TI4 inputs cannot clock the timer in this mode.
The clock signal fed into the TI1 or TI2 timer peripheral inputs is first conditioned before reaching the timer counter. The input conditioning is made of an external signal synchronization stage then a prescaling and filtering stage. The input filter and prescaler are configurable. The channel associated with the targeted timer input should be configured as an input channel; then the same control-bit fields used for configuring an input channel are used to configure the input for the external clocksource.
Below is the typical sequence to configure the TI1 or TI2 inputs as input for an external clock signal:
1. Configure the channel associated with the timer input that feeds the external clock signal as an input channel. （配置爲輸入並接到外部時鐘源）Even though any value written to the capture/compare selection (CCxS ) control bit-field except the 00 value sets the timer channel in input mode, the right value to configure is CCxS = 01.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
Note: The CCxS bit-field is writable only when its associated timer channel is disabled (for example when. the enable/disable control bit-field for that channel in the TIMx_CCER register is reset, CCxE = ‘0’.
2. Configure the active edge polarity（有效極性）. Some of the STM32 microcontrollers embed timers with inputs sensitive for either falling, rising or both edges (like STM32F2 microcontrollers); other STM32 families embed timers that have their inputs only sensitive for either rising or falling edges (like STM32F1 microcontrollers). The reference manual document for each STM32 microcontroller specifies the right value to write into the polarity control bit-fields to configure the convenient timer input polarity.
As an example, to make the timer input on STM32F30x microcontrollers sensitive to both edges, the polarity control bit-fields for the concerned channel should be configured as CCxP = 1 and CCxNP = 1. （上升、下降邊沿都有效）
3. If needed, configure the input filter associated with the concerned channel to reject pulses with duration shorter than a given value. The threshold for rejecting or passing the input pulse is configured through the ICxF[3:0] bit-field within the TIMx_CCMRx register associated to the used timer channel.
it 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
4. After having well configured the timer input with the required setting, redirect the conditioned input signal into the timer counter. This step is done by writing the right value into the trigger selection control bit-field TS[2:0] within the TIMx_SMCR register.
For instance, if the TI1 timer input is used as the external clock signal input, then the right configuration should be TS[2:0]=101.
Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0).
001: Internal Trigger 1 (ITR1).
010: Internal Trigger 2 (ITR2).
011: Internal Trigger 3 (ITR3).
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 86: TIMx Internal trigger connection for more details on ITRx meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
5. Finally, activate the external clock-source mode 1. This is done by writing the right value into the slave/master selection (SMS) bit-field within the TIMx_SMCR register. Note that this bit-field has different widths along the STM32 microcontroller families. The reference manual document specifies the right value to write to the SMS bit field inorder to activate the different clock modes.
For example, on the STM32F1 Series, the SMS bit filed is 3-bit wide and the right value to configure is SMS[2:0] = 111, whether for the STM32F30x microcontrollers the SMS bit-field is 4-bit wide and the right value to configure is SMS[3:0] = 0111.
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
6. Set the CEN control bit-field within the TIMx_CR1 register to enable the timer counter.
Figure 10 shows the typical counting sequence of the timer counter where the timer peripheral is configured in up-counting configuration. The counter content is null at the time of setting the CEN control bit-field, and the timer peripheral is externally clocked in mode 1 through its TI1 input.
This example shows that the configured active edge is the rising edge where the filter and prescaler control bit-fields are kept at their default value (like status after reset). Figure 10 also shows the effect of the resynchronization stage at the TI1 timer input.
There is a delay between the rising edge of the clock signal on the TI1 timer input and the rising edge of the internal counting signal fed into the timer counter CK_CNT. In this example the TIMx_PSC timer prescaler register content is null, so the CK_CNT signal is the same as CK_PSC signal (CK_CNT = CK_PSC).
The external clock-source mode 2
The main advantage of using the external clock-source mode 2 compared to mode 1 is that the externally provided clock signal frequency can be equal or even higher than the frequency of the internal timer core clock (like on APB bus clock).
This does not mean that the timer counter can be updated with a cadence higher than the timer core clock’s cadence (for example, incremented cadence if the timer is configured in up-counting mode).
The ETR timer input is the only timer input that features a presacler stage before the resynchronization stage. This presacaler stage is fully asynchronous and can be divided down to eight times less the asynchronous input signal frequency.
The output of the asynchronous prescaler stage, named ETRP signal, is routed to the resynchronization stage before being fed into the timer counter. The output of the resynchronization circuit is called ETRF signal. The ETRP signal has the same constraint as any other asynchronous signal fed to the timer, its frequency should be less than three times the timer internal core clock frequency.
This feature of the external clock-source mode 2 is of great interest in many applicative cases. For instance, it may be required to count the number of pulses generated by a certain sensor, but that sensor output frequency is higher than the timer internal core clock. In that case, the prescaler should be configured to scale down the input signal frequency by a given ratio that makes it compatible with the esynchronization stage constraint on external signal input frequency. When interpreting the counted pulse number, it should be taken into account that the signal frequency was divided by a given ratio.
Figure 11 shows an example where the timer peripheral is configured in external clocksource mode 2 and where the clock signal is fed into the timer through its ETR input. In this example the external clock signal frequency is higher than the timer internal core clock (the APB bus clock). The ETR asynchronous prescaler was configured to divide the input signal frequency by four by setting the external trigger prescaler control bit-field within the TIMx_SMCR register to ETPS = ‘10’.
Also, Figure 11 shows a delay between the output of the prescaler (ETRP signal) and the counter clock signal CK_CNT used to update the timer counter. This delay is inserted by the resynchronization stage.
Below is the typical and recommended sequence to configure the timer peripheral in external clock-source mode 2:
1. Evaluate the maximum frequency of the input clock signal and choose the asynchronous prescaler ratio. If the external clock signal frequency is less than the timer internal core clock by more than three times, then the use of the prescaler is optional and may not be used. In the case that the asynchronous prescaler is not used, the ETPS control bit-filed should be reset (the ETPS bit-filed is by default reset).
prescaler在外部信號少於3倍頻於內部時鐘信號的時候不要使用。
Bits 13:12 ETPS: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
2. If required, activate the filtering stage to reject clock signal pulses with duration shorter than a certain threshold. For more information on how to set up the filter feature on the STM32 timer peripheral external inputs, refer to Section 1.4.1: Filtering stage on page 12.
然後，輸入可以過濾掉一些短的干擾波形，這個可以設定
3. Configure the active edge of the external clock signal. The ETP control-bit sets for which the external clock-source mode 2 edge is sensitive. By default and after reset, the ETP control-bit is reset, which makes the external clock signal rising edges for the active ones (for example rising edges of the external clock signal triggers the timer counter update).
Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
4. Enable the external clock-source mode 2 by setting the external clock enable control bit, ECE =1.
5. It is mandatory（必須的）, at the end to set the counter enable control bit within the TIMx_CR1 register to enable the timer counter.
Note: The ETR input can be used also as an input for the external clock signal when the external clock-source mode 1 is configured. It is possible to activate both the external clock-source mode 1 and 2 simultaneously and make them use simultaneously the ETR input. In that case the priority is given to the external clock-source mode 2 and it is the one used for clocking the timer counter.
External clock-source mode 1 versus mode 2
Both external clock-source modes, 1 and 2, seem to have the same functionality but studying them carefully shows that they differ in some specific characteristics that makes each one of them suitable for a different range of applicative cases.
See below the main differences between mode 1 and 2:
• It is possible to use the external source clock mode 1 to update the timer counter on both edges of the external clock signal. This is not possible when the external clocksource mode 2 is used.
• By using external clock-source mode 2, it is possible to clock the timer peripheral by an external clock-source. It is then still possible to configure the timer peripheral, at the same time, in one of the compatible timer slave modes. For example, if it is required to count the number of pulses generated by certain sensor within a given period of time repeatedly:
– Make one timer peripheral, like TIMy, count the number of pulses generated by the sensor by configuring it in external clock-source mode 2.
– By configuring a second timer peripheral, like TIMz, to generate a trigger-out signal (TRGO) each given period of time, repeatedly.
– The first timer (TIMy) should be configured also in slave reset mode and use the TRGO output signal of the second timer (TIMz) as trigger for the reset.
One way to make a timer peripheral output a pulse on its TRGO output signal at regular time intervals is by setting the TIMx_ARR timer register to a certain value so a periodic timer “update event” is generated. A timer “update event” can trigger a pulse on the timer’s TRGO signal if the timer master mode is set to “update value” (for example if MMS[2:0] bit-filed is set to ‘010’ within the TIMx_CR2 register).
A timer may be configured in reset slave mode by setting the right value in the slave mode selection control bit-field (for example SMS[2:0] = 100 within the TIMx_SMCR register).
Selecting the right trigger for the reset slave mode is ensured by configuring the right value into the trigger selection control bit-field TS[2:0].
The value to write into TS[2:0] control bit-filed depends on which ITR timer input of the first timer (TIMy) the TRGO output of the second timer (TIMz) is internally connected to. The reference manual of each STM32 microcontroller lists all the internal interconnections between timer peripherals.