前言：直接開講，請耐心看完 ：
首先,OPM模式的波形可以通過主從模式進行觸發，其次，OPM模式的波形本身可以進行波形定製。
1 OPM定義和功能說明
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
OPM 模式是一個比較特殊的模式，該模型的參數包括：可以定製的長度和Delay（相位）的波形
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode.
定時器的觸發可以通過主從模式的定時器來控制，而輸出波形可以是CC模式或者PWM模式。
Select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
在TIMx_CR1選擇OPM模式使能OPM,同時定時器的計數器在下一個Event UEV停止計數
2 OPM設定的定時器通道相關控制寄存器：
2.1 OPM-使能-定時器控制寄存器：
TIM1 and TIM8 control register 1 (TIMx_CR1)
OPM模式，其實就是在一個脈衝波形後暫停計數，就這麼簡單，後面也方便你定製。
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
2.2 OPM-波形的設定：
使能OPM之後，後面就是對OPM的輸出波形進行設置：波形的設定，用CC(捕捉比較）的方式， 就是用定時器的計數去比較你的各種設定，然後，各種翻轉邏輯，最後實現波形的定製。
A pulse can be correctly generated only if the compare value is different from the counter initial value.
後面要做的事情就是CNT(counter的計數）和CCRx \ ARR進行比較，當然在比較之前，如下：
Before starting (when the timer is waiting for the trigger), the configuration must be:
（向上計數的時候）CNT的計數應該小於CCRX或 ARR這樣才能產生波形。
• In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)
• In downcounting: CNT > CCRx
2.2.1 設定輸出波形的細節
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
我們知道CCR爲CC模式的比較值，這個值來決定Delay也就是相位
• The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).
自動裝載值和比較值之間的差值用了決定脈寬
• Let us say the user wants to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value.
我們假設我們的波形在CC模式比較匹配時候爲高電平翻轉，而當定時器計數達到自動裝載值的時候爲低電平翻轉。所謂CC模式比較匹配，就是CNT = CCRx,這時候電平翻轉到高，定時器計數達到自動裝載值，就是CNT = ARR的時候，高電平變成低電平下圖做了一些修改，原圖遺失CCR1的橫座標線
對於輸出的波形有多種選擇，
To do this, enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register.
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
The user can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register.
Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
In this case the compare value must be written in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2.
（STM32手冊這裏好像有錯誤，應該是CC2P，不是CC1P）CC2P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
Bit 4 DIR: Direction 0: Counter used as upcounter
The user only wants one pulse (Single mode), so '1’ must be written in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable:
OPM模式也可以轉成多波複製的模式，只需要OPM 位設爲0即可。
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get.
侷限性：就是Delay的最小時間是系統侷限的，因爲上述信號接入需要一點時間：
If the user wants to output a waveform with the minimum delay, the OCxFE bit in the TIMx_CCMRx register must be set. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
注意：
要立即響應的得到最小Delay的話，需要使能OCXFE位，改位用來強制OCx對OCXREF的響應加速。
這個代價換來的意義是，多了僅僅兩個時鐘週期的響應時間。
For example the user may want to generate a positive pulse on OC1 （輸出比較）with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
2.3 設置觸發和時鐘通道，定時器信號通道選擇：
-
Let’s use TI2FP2 as trigger 1:
選擇觸發信號：下圖爲Timer channel的圖
我們這樣理解定時器通道，定時器通道分成兩個部分：輸入、輸出
輸入的部分我們看：
TI1 、TI2這些都是input，輸入通道包括輸入濾波（可以濾除小的脈衝）和邊沿檢測，這樣就到了TIxFPx（也就是輸入經過濾波和預分頻檢測後的波形，叫做TI2FP2 Filtered Timer2 Input 2）。然後是，
IC1,input capture輸入捕捉通道，也屬於輸入吧，這裏又有在預分頻後的信號叫，ICx,(每個信號給他定一個名稱就是爲了後面負責的通道組合做好標識）。然後是，
OC,輸出比較通道，現在開始算輸出通道。在進入輸出通道OC之前，要開始做複雜的波形運算，達到我們想要的波形。就必須通過捕捉比較寄存器。通過設定通道的OCXREF、DTG的給到輸出通道。
• Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
將定時器輸入通道TI2連接到TI2FP2,實際上是啓用了CH2,
將
通道設定之後，通道的輸出也就設定好了。
• TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register.
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
• Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register.
準備將TI2FP2作爲從控制器的輸入：
TIM1 and TIM8 slave mode control register (TIMx_SMCR)
Bits 6:4 TS[2:0]: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
• TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode).
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
最後，來一個重點中的重點，相位調節示意圖：
