前言：時基是定時器的最基本的功能：
本節詳細敘述STM32的時基的功能。
1 Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIMx_CNT)計數器
• Prescaler register (TIMx_PSC) 分頻設定寄存器值
• Auto-reload register (TIMx_ARR) 自動裝載寄存器值
• Repetition counter register (TIMx_RCR) 自動裝載重複計數寄存器
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
每個UEV，ARPE的值是可以改變的。
The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register.
It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.
2 Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly(即時生效） as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
案：由於改變是實時的，分頻器的改變可以在下一個事件更新時候就生效
Figure 53 and Figure 54 give some examples of the counter behavior when the prescaler ratio is changed on the fly:
3 Counter modes
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
ARR是將被實際裝載的寄存器的值
If the repetition counter（重複計數使能） is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
在重複計數模式下，UEV的產生：在重複計數器寄存器達到重複寄存器值+1的時候產生，注意這時候的計數是計的upcounting is repeated，也就是自動裝載計數器重複裝載的數值。
RCR是重複計數值，
（
簡單說明一下RCR,RCR就是重複裝載計數，這個在比較寄存器那裏，理解爲更新率。
REP的計數都是向下計數到0的，那麼，每一次更新事件就會重新計數到之前REP的值。同時產生 U_RC的事件。
寫到 RCR的值都只會在下一個週期的時候起作用。
）
Else the update event is generated at each counter overflow.
如果repetition counter不計數，每次自動裝載都會產生溢出事件。
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event（產生事件但是不一定產生中斷）. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG(Update Generation from TIMx_EGR) bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
這個位控制事件的發生時候，中斷是否產生。
When an update event occurs, all the registers are updated and the update flag (UIF（Update interrupt flag ） bit in TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register,
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
