參考博客:
https://blog.csdn.net/lg2lh/article/details/45375317
https://blog.csdn.net/lg2lh/article/details/45220283
BUFR是區域時鐘緩衝器,要進入區域時鐘網絡,必須例化BUFR。
BUFR #(
.BUFR_DIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
.SIM_DEVICE("7SERIES") // Must be set to "7SERIES"
)
BUFR_inst (
.O(O), // 1-bit output: Clock output port
.CE(CE), // 1-bit input: Active high, clock enable (Divided modes only)
.CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
.I(I) // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
module util_clkdiv (
input clk,
input clk_sel,
output clk_out
);
parameter SIM_DEVICE = "7SERIES";
parameter SEL_0_DIV = "4";
parameter SEL_1_DIV = "2";
wire clk_div_sel_0_s;
wire clk_div_sel_1_s;
generate if (SIM_DEVICE == "7SERIES") begin
BUFR #(
.BUFR_DIVIDE(SEL_0_DIV),
.SIM_DEVICE("7SERIES")
) clk_divide_sel_0 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_sel_0_s));
BUFR #(
.BUFR_DIVIDE(SEL_1_DIV),
.SIM_DEVICE("7SERIES")
) clk_divide_sel_1 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_sel_1_s));
end else if (SIM_DEVICE == "ULTRASCALE") begin
BUFGCE_DIV #(
.BUFGCE_DIVIDE(SEL_0_DIV)
) clk_divide_sel_0 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_sel_0_s));
BUFGCE_DIV #(
.BUFGCE_DIVIDE(SEL_1_DIV)
) clk_divide_sel_1 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_sel_1_s));
end endgenerate
BUFGMUX_CTRL i_div_clk_gbuf (
.I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
.I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1)
.S(clk_sel),
.O (clk_out));
endmodule // util_clkdiv