2440學習筆記

S3C2440有兩個PLL：MPLL和UPLL，UPLL專用與USB設備。MPLL用於CPU及其他外圍器件。
通過MPLL會產生三個部分的時鐘頻率：FCLK、HCLK、PLCK。FCLK用於CPU核，HCLK用於AHB總線的設備(比如SDRAM)，PCLK用於APB總線的設備(比如UART)。
FCLK is used by ARM920T.
HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD
controller, the DMA and USB host block.
PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface,
ADC, UART, GPIO, RTC and SPI.


The S3C2440A has two Phase Locked Loops (PLLs):
one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz).

AMBA(Advanced Micro controller Bus Architecture)規範主要包括了AHB(Advanced High performance Bus)系統總線和APB(Advanced Peripheral Bus)外圍總線。

CPSR (Current Program Status Register).This contains condition code flags and the current mode bits.
N, 31: Negative/Less Than
Z, 30: Zero
C, 29: Carry/Borrow/Extend
V, 28: Overflow

Saved Process Status Registers (SPSR)

stack pointer register (SP)
link register (LR)
Program Counter (PC)

The ARM State Register Set:
Register 14: This register is used as the subroutine link register. This receives a copy of R15 when a BL instruction is executed.
Register 15: This register holds the Program Counter (PC).
Register 16: This register is the CPSR (Current Program Status Register).

Memory Management Unit (MMU)
Software Interrupt Instruction (SWI), is used for entering Supervisor mode.

算術邏輯單元 (ALU), 是中央處理器(CPU)的執行單元，是所有中央處理器的核心組成部分.

;ARM的系統軟件開發中主要包含RO，RW,ZI三個段組成。
;其中RO爲代碼段；RW爲已經初始化的全局變量；ZI是未初始化的全局變量

Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to
set the condition codes on the result and always have the S bit set.
 
ARM Instruction Set P99

BUS WIDTH & WAIT CONTROL REGISTER (BWSCON)

SRAM是英文Static RAM的縮寫，它是一種具有靜止存取功能的內存，不需要刷新電路即能保存它內部存儲的數據。而DRAM（Dynamic Random Access Memory)每隔一段時間，要刷新充電一次，否則內部的數據即會消失，因此SRAM具有較高的性能。

SROM means ROM or SRAM type memory

USB host interface and USB device interface needs 48Mhz clock.

前綴表示法：
    ldr r5, [r6, #4]  ; r5 <- [r6 + 4]
    str r3, [r4, #8]  ; r3 -> [r4 + 8]
後綴表示法：
    ldr    r3, [r0], #4  ; r3 <- [r0], r0 <- r0 + 4
    str    r3, [r1], #4  ; r3 -> [r1], r1 <- r1 + 4

EINT0 - EINT23: GPF0 - GPF7, GPG0 - GPG15    (24個)
If GPF0–GPF7 or GPG0 - GPG15 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode.   
GPG[15:13] must be selected as Input in NAND boot mode.

To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the
noise filter.

使用ldr說明絕對地址, 使用adr/adrl說明相對地址。

arm-linux-gcc的配置：
1. http://www.handhelds.org/download/projects/toolchain/下載arm-linux-gcc-3.4.1.tar.bz2,並解壓縮；
2. edit /etc/profile 加入環境變量PATH.
   #Kenny: for arm board support.
   export PATH=$PATH:/home/sea/work/arm/arm-linux-gcc-3.4.1/usr/local/arm/3.4.1/bin

Norflash的型號爲Eon的EN29LV160AB。  
P243