輸入01字符串，計算01字符串累加和，如果和是3的倍數，輸出is_triple拉高

採用模3除法實現需要調用觸發器且會引入延時，耗時太長的同時也會漏掉某些值。本文給出一種通用的模N(3)除法運算的簡化版解決辦法，只需簡單邏輯即可實現；

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:44:53 09/24/2019 
// Design Name: 
// Module Name:    test_triple 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test_triple(
   input clk,
	input rst_n,
	input x,
	output x_reg,
	output is_triple
    );
	reg [1:0] count;
	reg is_triple_flag;
	
	always@(posedge clk or negedge rst_n)begin
	   if(!rst_n)begin
		  count <= 0;
		end
		else begin
		  if((count == 2'b11)&&(x == 1'b1))begin
		     count <= 2'd1;
		  end
		  else begin
		     count <= count + x;
		  end
		end
	end
	
	always@(posedge clk or negedge rst_n)begin
	   if(!rst_n)begin
		  is_triple_flag <= 0;
		end
		else begin
		  if(count == 2'b11)begin
		    is_triple_flag <= 1'b1;
		  end
		  else begin
		    is_triple_flag <= 1'b0;
		  end
		end
	end
	reg x_q;
	always@(posedge clk or negedge rst_n)begin
	   if(!rst_n)begin
		  x_q <= 0;
		end
		else begin
        x_q <= x;
		end
	end
	assign x_reg = x_q;
	assign is_triple = is_triple_flag;

endmodule

testbench如下：

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:02:24 09/24/2019
// Design Name:   test_triple
// Module Name:   D:/E_lerning/2017labxm/selflearning_pro/is_triple/is_triple/tb_triple.v
// Project Name:  is_triple
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: test_triple
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_triple;

	// Inputs
	reg clk;
	reg rst_n;
	reg x;

	// Outputs
	wire x_reg;
	wire is_triple;

	// Instantiate the Unit Under Test (UUT)
	test_triple uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.x(x), 
		.is_triple(is_triple)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;
		x = 0;

		// Wait 100 ns for global reset to finish
		#100;
      rst_n = 1;
		// Add stimulus here

	end
	
	parameter period = 40;    //25M
   always begin
     clk=0;
	  #(period/2) clk=1;
	  #(period/2) clk=0; 
   end
	
   reg [3:0]count_tb;
	always@(posedge clk or negedge rst_n)begin
     if(!rst_n)begin
	    count_tb <= 0;
	  end
	  else begin
	    count_tb <= count_tb + 1;
	  end
   end	
	
	always@(posedge clk or negedge rst_n)begin
	  if(!rst_n)begin
	  end
	  else begin
	    case(count_tb)
		     0,1,6:x<=0;
			  default begin
			     x<=1;
			  end	 
		 endcase
	  end
	end
		
		

endmodule

modelsim仿真結果如下：

x_q爲打了一拍後的輸入序列；

count是計數信號；

is_triple是輸出結果