關於時鐘輸入引腳爲n時的調試

1、在xilinx fpga中，當輸入時鐘爲單端時，手冊上推薦時鐘輸入引腳爲p，當輸入時鐘引腳爲n時會對系統造成什麼樣的影響
2、新建工程
源碼
module clk_test(
input wire clk_sys,
output wire clk_out1,
input wire clk_in1,
output wire clk_out2
);

wire clk_out1_bufg;

clk_wiz_0 clk_wiz_0_inst(
.clk_out1(clk_out1_bufg),
.clk_sys(clk_sys)
);

ODDR#(
.DDR_CLK_EDGE(“OPPOSITE_EDGE”), // “OPPOSITE_EDGE” or “SAME_EDGE”
.INIT(1’b0), // Initial value of Q: 1’b0 or 1’b1
.SRTYPE(“SYNC”) // Set/Reset type: “SYNC” or “ASYNC”
)
ODDR1_inst (
.Q(clk_out1), // 1-bit DDR output
.C(clk_out1_bufg), // 1-bit clock input
.CE(1’b1), // 1-bit clock enable input
.D1(1’b0), // 1-bit data input (positive edge)
.D2(1’b1), // 1-bit data input (negative edge)
.R(1’b0), // 1-bit reset
.S(1’b0) // 1-bit set
);

wire clk_in1_bufg;

BUFG BUFG_inst (
.O(clk_in1_bufg), // 1-bit output: Clock output
.I(clk_in1) // 1-bit input: Clock input
);

ODDR#(
.DDR_CLK_EDGE(“OPPOSITE_EDGE”), // “OPPOSITE_EDGE” or “SAME_EDGE”
.INIT(1’b0), // Initial value of Q: 1’b0 or 1’b1
.SRTYPE(“SYNC”) // Set/Reset type: “SYNC” or “ASYNC”
)
ODDR2_inst (
.Q(clk_out2), // 1-bit DDR output
.C(clk_in1_bufg), // 1-bit clock input
.CE(1’b1), // 1-bit clock enable input
.D1(1’b0), // 1-bit data input (positive edge)
.D2(1’b1), // 1-bit data input (negative edge)
.R(1’b0), // 1-bit reset
.S(1’b0) // 1-bit set
);
3、
4、管腳約束
set_property PACKAGE_PIN B17 [get_ports clk_out1]
set_property PACKAGE_PIN A17 [get_ports clk_in1]
set_property PACKAGE_PIN F22 [get_ports clk_sys]
set_property PACKAGE_PIN A18 [get_ports clk_out2]
set_property IOSTANDARD LVCMOS33 [get_ports clk_in1]
set_property IOSTANDARD LVCMOS33 [get_ports clk_out1]
set_property IOSTANDARD LVCMOS33 [get_ports clk_out2]
set_property IOSTANDARD LVCMOS33 [get_ports clk_sys]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_in1]
5、大致說明 全局時鐘輸入25Mhz，clk_out1輸出50Mhz，板卡飛線clk_out1 ——>clk_in1 這樣就完成了p輸出n輸入，完成後理論上clk_out2的輸出也應該時50Mhz輸出。
6、將程序下載到板卡，示波器測量clk_out2。

7、可知並未對功能造成實質的影響
8、目測問題就是時序不太好。
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin © a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
9、