ISE中進行綜合後，查看生成的report，找到Timing Report部分。簡要分析如下：
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATIONPLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
ClockSignal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk |BUFGP | 1699 |
coef/N0 | NONE(coef/BU308) |15 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were notautomatically buffered by XST with BUFG/BUFR resources. Please usethe buffer_type constraint in order to insert these buffers to theclock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------+----------------------------------+-------+
ControlSignal | Buffer(FFname) | Load |
---------------------------------------------------------+----------------------------------+-------+
coef/N0(coef/GND:G) |NONE(coef/BU11) | 60 |
fir/blk00000003/chan_in(0)(fir/blk00000003/blk00000004:G)|NONE(fir/blk00000003/blk00000a0f)| 24 |
reset_inv(reset_inv1_INV_0:O) |NONE(cnt_9) | 17 |
---------------------------------------------------------+----------------------------------+-------+
Timing Summary:
---------------
Speed Grade: -12
Minimum period: 2.956ns (Maximum Frequency:338.289MHz)
Minimum input arrival time before clock: 2.327ns
Maximum output required time after clock: 3.874ns
Maximum combinational path delay: No path found
上述四條信息即爲靜態時序分析中的4個要點，分別爲：
最小週期，即最大工作頻率；
最小輸入數據建立時間，可理解爲數據信號的建立時間（從FPGA外部看進來），該時間只針對模塊的輸入數據信號有效，即表示模塊外部輸入的數據在時鐘信號有效沿到來前應該保持穩定不變的最小時間。
最大輸出數據時間，表示從對數據賦值的clk有效沿開始，模塊輸出管腳達到穩定的最大時間，該時間只對模塊的輸出信號有效。
最大組合邏輯延遲時間，該時間可作爲關鍵路徑延遲時間，若不存在關鍵路徑，則不顯示。
針對上述4點可大概估計設計的最大工作頻率，以及影響最大工作頻率提高的關鍵路徑，進一步根據以下信息確定關鍵路徑，從而對關鍵路徑進行優化，以提高最大工作頻率。而最小輸入數據建立時間可作爲對模塊輸入數據的時序要求，爲了提高模塊性能，往往希望該時間越短越好，可進一步根據以下信息確定影響該時間的路徑，加以優化。
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.956ns (frequency: 338.289MHz)
Total number of paths / destination ports: 11500 / 4354
這部分提到的信號及其具體延遲信息，就是影響模塊最大工作頻率的關鍵信號和路徑，若想進一步提高模塊工作頻率，可針對該信號或路徑進行優化。
-------------------------------------------------------------------------
Delay: 2.956ns (Levels of Logic = 5)
Source: coef/BU13 (RAM)
Destination: fir/blk00000003/blk000007c7 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: coef/BU13 to fir/blk00000003/blk000007c7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (NetName)
---------------------------------------- ------------
RAMB16:CLKA->DOPA0 1 1.647 0.554 BU13 (N364)
LUT4:I0->O 1 0.147 0.000 BU246 (N8760)
MUXF5:I0->O 1 0.291 0.000 BU252 (N8655)
MUXF6:I1->O 1 0.300 0.000 BU254 (dout<8>)
end scope: 'coef'
begin scope: 'fir'
begin scope: 'blk00000003'
FDRE:D 0.017 blk000007c7
----------------------------------------
Total 2.956ns (2.402ns logic, 0.554ns route)
(81.3% logic, 18.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 74 / 74
這一部分提到的信號及其延遲信息，就是影響最小輸入數據建立時間的關鍵信號或者路徑，若要減小該時間，可針對這些信號或路徑進行優化。
-------------------------------------------------------------------------
Offset: 2.327ns (Levels of Logic = 2)
Source: reset (PAD)
Destination: coef_ram_addr_init_0 (FF)
Destination Clock: clk rising
Data Path: reset to coef_ram_addr_init_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (NetName)
---------------------------------------- ------------
IBUF:I->O 16 0.754 0.609 reset_IBUF(reset_IBUF)
LUT2:I0->O 14 0.147 0.409 coef_ram_addr_init_and00001 (coef_ram_addr_init_and0000)
FDE:CE 0.409 coef_ram_addr_init_0
----------------------------------------
Total 2.327ns (1.310ns logic, 1.017ns route)
(56.3% logic, 43.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 42 / 42
同理，這一部分提到的信號及其延遲信息是影響模塊數據最大輸出時間的關鍵。
-------------------------------------------------------------------------
Offset: 3.874ns (Levels of Logic = 2)
Source: fir/blk00000003/blk0000089b (FF)
Destination: rfd (PAD)
Source Clock: clk rising
Data Path: fir/blk00000003/blk0000089b to rfd
Gate Net
Cell:in->out fanout Delay Delay Logical Name (NetName)
---------------------------------------- ------------
FDSE:C->Q 9 0.272 0.347 blk0000089b (rfd)
end scope: 'blk00000003'
end scope: 'fir'
OBUF:I->O 3.255 rfd_OBUF (rfd)
----------------------------------------
Total 3.874ns (3.527ns logic, 0.347ns route)
(91.0% logic, 9.0% route)
=========================================================================
上述時鐘分析只是綜合後的時序，與最終硬件上跑的時序是有差別的。關於最小數據輸入時間和最大數據輸出時間的定義以及其他相關內容可參考以下博客內容：http://blog.ednchina.com/cqcrr/143490/message.aspx