請 尊重作者，勿 轉載，謝謝 ~
簡介
編者使用 Quartus II 9.0 進行編程，使用 VHDL語言 ，主要實驗有兩個，分別是基於芯片 MAX7000S: EPM7128SLC84-15的硬佈線和流水硬連線。
流程圖
- 硬連線 ：
![在這裏插入圖片描述]()
- 流水硬連線 ：
![在這裏插入圖片描述]()
- 模型機流程圖 ：
![在這裏插入圖片描述]()
引腳配置
如圖：
添加的功能
-
在原指令基礎上要求擴指至少三條： 硬佈線添加三條，流水添加四條
-
修改PC指針功能（任意指針）
測試程序及檢測結果
直接檢測流水，相關如圖：
代碼（VHDL語言）
1.硬佈線
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Duang IS PORT ( SWB : IN STD_LOGIC; SWA : IN STD_LOGIC; SWC : IN STD_LOGIC; clr : IN STD_LOGIC; C : IN STD_LOGIC; Z : IN STD_LOGIC; IRH : IN STD_LOGIC_VECTOR(3 DOWNTO 0); T3 : IN STD_LOGIC; W1 : IN STD_LOGIC; W2 : IN STD_LOGIC; W3 : IN STD_LOGIC; SELCTL : OUT STD_LOGIC; ABUS : OUT STD_LOGIC; M : OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SEL1 : OUT STD_LOGIC; SEL0 : OUT STD_LOGIC; SEL2 : OUT STD_LOGIC; SEL3 : OUT STD_LOGIC; DRW : OUT STD_LOGIC; SBUS : OUT STD_LOGIC; LIR : OUT STD_LOGIC; MBUS : OUT STD_LOGIC; MEMW : OUT STD_LOGIC; LAR : OUT STD_LOGIC; ARINC : OUT STD_LOGIC; LPC : OUT STD_LOGIC; PCINC : OUT STD_LOGIC; PCADD : OUT STD_LOGIC; CIN : OUT STD_LOGIC; LONG : OUT STD_LOGIC; SHORT : OUT STD_LOGIC; QD : IN STD_LOGIC; STOP : OUT STD_LOGIC; LDC : OUT STD_LOGIC; LDZ : OUT STD_LOGIC ); END Duang; ARCHITECTURE art OF Duang IS SIGNAL SWCBA : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL ST0 : STD_LOGIC; SIGNAL ST0_reg : STD_LOGIC; SIGNAL SST0 : STD_LOGIC; SIGNAL STOP_reg_reg : STD_LOGIC; SIGNAL STOP_reg : STD_LOGIC; BEGIN STOP <= (STOP_reg_reg OR STOP_reg) WHEN (SWCBA /= "000") ELSE '0'; SWCBA(2 DOWNTO 0) <= (SWC & SWB & SWA); ST0 <= ST0_reg; PROCESS (clr, T3) BEGIN IF (clr = '0') THEN ST0_reg <= '0'; STOP_reg_reg <= '1'; ELSIF (T3'EVENT AND T3 = '0') THEN IF (SST0 = '1') THEN ST0_reg <= '1'; END IF; END IF; END PROCESS; PROCESS (SWCBA, IRH, W1, W2, W3, ST0, C, Z) BEGIN SHORT <= '0'; LONG <= '0'; CIN <= '0'; SELCTL <= '0'; ABUS <= '0'; SBUS <= '0'; MBUS <= '0'; M <= '0'; S <= "0000"; SEL3 <= '0'; SEL2 <= '0'; SEL1 <= '0'; SEL0 <= '0'; DRW <= '0'; SBUS <= '0'; LIR <= '0'; MEMW <= '0'; LAR <= '0'; ARINC <= '0'; LPC <= '0'; LDZ <= '0'; LDC <= '0'; STOP_reg <= '1'; PCINC <= '0'; SST0 <= '0'; PCADD <= '0'; CASE SWCBA IS WHEN "000" => IF (ST0 = '0') THEN LPC <= W1; SBUS <= W1; SST0 <= W1; SHORT <= W1; STOP_reg <= '0'; ELSIF (ST0 = '1') THEN CASE IRH IS WHEN "0001" => --ADD LIR <= W1; PCINC <= W1; S <= "1001"; CIN <= W2; ABUS <= W2; DRW <= W2; LDC <= W2; LDZ <= W2; WHEN "0010" => --SUB LIR <= W1; PCINC <= W1; S <= "0110"; ABUS <= W2; DRW <= W2; LDZ <= W2; LDC <= W2; WHEN "0011" => --AND LIR <= W1; PCINC <= W1; S <= "1011"; M <= W2; ABUS <= W2; DRW <= W2; LDZ <= W2; WHEN "0100" => --INC LIR <= W1; PCINC <= W1; S <= "0000"; ABUS <= W2; DRW <= W2; LDZ <= W2; LDC <= W2; WHEN "0101" => --LD LIR <= W1; PCINC <= W1; S <= "1010"; M <= W2; ABUS <= W2; LAR <= W2; LONG <= W2; MBUS <= W3; DRW <= W3; WHEN "0110" => --ST LIR <= W1; PCINC <= W1; M <= W2 OR W3; S(3) <= '1'; S(2) <= W2; S(1) <= '1'; S(0) <= W2; ABUS <= W2 OR W3; LAR <= W2; LONG <= W2; MEMW <= W3; WHEN "0111" => --JC LIR <= W1; PCINC <= W1; PCADD <= C AND W2; WHEN "1000" => --JZ LIR <= W1; PCINC <= W1; PCADD <= Z AND W2; WHEN "1001" => --JMP LIR <= W1; PCINC <= W1; M <= W2; S <= "1111"; ABUS <= W2; LPC <= W2; WHEN "1010" => --OUT M <= W2; S <= "1010"; ABUS <= W2; WHEN "1011" => --OR LIR <= W1; PCINC <= W1; M <= W2; S <= "1110"; ABUS <= W2; DRW <= W2; LDZ <= W2; WHEN "1100" => --NOT LIR <= W1; PCINC <= W1; M <= W2; S <= "0000"; ABUS <= W2; DRW <= W2; LDZ <= W2; WHEN "1101" => --A*2+1 LIR <= W1; PCINC <= W1; S <= "1100"; ABUS <= W2; DRW <= W2; LDZ <= W2; LDC <= W2; WHEN "1110" => --STP LIR <= W1; PCINC <= W1; STOP_reg <= W2; WHEN OTHERS => LIR <= W1; PCINC <= W1; END CASE; END IF; WHEN "001" => SELCTL <= W1; SHORT <= W1; SBUS <= W1; STOP_reg <= W1; SST0 <= W1; LAR <= W1 AND (NOT(ST0)); ARINC <= W1 AND ST0; MEMW <= W1 AND ST0; WHEN "010" => SELCTL <= W1; SHORT <= W1; SBUS <= W1 AND (NOT(ST0)); MBUS <= W1 AND ST0; STOP_reg <= W1; SST0 <= W1; LAR <= W1 AND (NOT(ST0)); ARINC <= W1 AND ST0; WHEN "011" => SELCTL <= '1'; STOP_reg <= W1 OR W2; SEL3 <= W2; SEL2 <= '0'; SEL1 <= W2; SEL0 <= W1 OR W2; WHEN "100" => SELCTL <= '1'; SST0 <= W2; SBUS <= W1 OR W2; STOP_reg <= W1 OR W2; DRW <= W1 OR W2; SEL3 <= (ST0 AND W1) OR (ST0 AND W2); SEL2 <= W2; SEL1 <= ((NOT(ST0)) AND W1) OR (ST0 AND W2); SEL0 <= W1; WHEN OTHERS => END CASE; END PROCESS; END art;
2.流水
相信聰明如你，應該能寫出流水了吧，小編實在太困了，就不放代碼啦（不然要慢慢排版呢
\n //手動換行嘿嘿
如果真的需要流水的代碼的話就下載叭，我已經上傳過了，文件名稱爲Duangg.vhd，鏈接爲：https://download.csdn.net/download/hongwangdb/11225811
還有什麼問題可以私小編嗷
