Quartus常見錯誤分析

1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list
 
----沒把singal放到process（）中

2 Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
 
-=-----可能是說設計中產生的觸發器沒有使能端

3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
  ------信號類型設置不對，out當作buffer來定義

4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"
  -------引用的例化元件未定義實體－－entity "clk_gen"

5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
 Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
 Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer

6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.

7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
   -----缺少敏感信號

8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register

9  Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND

10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.

11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.

12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"
------兩者不能連接起來

13  Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.
 ------沒有編寫testbench文件，或者沒有編輯輸入變量的值  testbench裏是元件申明和映射

14  Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component
  ---在相關的元件裏沒有當前文件所定義的類型

15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does not hold its outside clock edge

16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"

17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node.
  ---"temp[19]"被優化掉了

18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND

19 Warning: Design contains 2 input pin(s) that do not drive logic
 Warning: No output dependent on input pin "clk"
 Warning: No output dependent on input pin "sign"
  ------輸出信號與輸入信號無關，

20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"

21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"

22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared
-------連接表錯誤，形參"alarm"賦值給實參，形參沒定義，可能是形參與實參的位置顛倒了，規定形參在實參之前。

23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors
－－－－－－－－因爲前一個錯誤而導致的錯誤

24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type
－－－－－－－－"alarm"的定義類型與使用的類型不一致

25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks
  -------同一進程中含有兩個或多個if(edge)條件，（一個進程中之能有一個時鐘沿）

26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19)

27  can't infer register for signal "num[0]" because signal does not hold its outside clock edge

28Error: Can't elaborate top-level user hierarchy

29 Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32)     ----------有兩個以上賦值語句，不能確定“cs_in”的值，

30 Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.
---------------在源文件中找不到對應的節點“over”。

31 Error: Can't access JTAG chain
     無法找到下載鏈
32  Info: Assuming node "clk" is an undefined clock