//**************************mux_8.v**************************************
module mux_8(mout, addr, in1, in2, in3, in4, in5, in6, in7, in8,ena);
input[3:0] in1, in2, in3, in4, in5, in6, in7, in8;
input ena;
input[2:0] addr;
output[3:0] mout;
reg[3:0] mout;
always @(in1 or in2 or in3 or in4 or in5 or in6 or in7 or in8 or addr or ena)
begin
if(!ena) //使能信號ena低電平有效
case(addr)
3'b000: mout=in1;
3'b001: mout=in2;
3'b010: mout=in3;
3'b011: mout=in4;
3'b100: mout=in5;
3'b101: mout=in6;
3'b110: mout=in7;
3'b111: mout=in8;
endcase
else mout=4'bx;
end
endmodule
//*****************************mux_8_TB.v******************************
`timescale 1ns / 1ns
module mux_8_TB;
reg[3:0] in1, in2, in3, in4, in5, in6, in7, in8;
reg ena;
reg[2:0] addr;
wire[3:0] mout;
initial
begin
ena=0;
in1=0;
in2=0;
in3=0;
in4=0;
in5=0;
in6=0;
in7=0;
in8=0;
addr= 3'b000;
repeat(5)
#10 begin
in1={$random}%16;
in2={$random}%16;
in3={$random}%16;
in4={$random}%16;
in5={$random}%16;
in6={$random}%16;
in7={$random}%16;
in8={$random}%16;
addr=addr+1;
end
#10 $stop;
end
mux_8 m1(mout, addr, in1, in2, in3, in4, in5, in6, in7, in8,ena);
endmodule