三分頻電路
module half_clk(reset, clk_in, clk_out);
input reset, clk_in;
output clk_out;
reg clk_out;
reg[1:0] cnt;
always @(posedge clk_in or negedge clk_in)
begin
if(!reset)
begin
cnt <= 2'b00;
clk_out <= 0;
end
else
if(cnt==2)
begin
cnt<=2'b00;
clk_out <= ~clk_out;
end
else cnt <= cnt+1;
end
endmodule
如果想實現n分頻,把cnt==2換成cnt==n-1即可,當然cnt的位數也要隨之改變,至少能表示n-1吧。同時將clk_out延遲一個clk_in輸出可有效減少毛刺現象的影響(倒數第二行加一句clk_out1 <= clk_out)。
六分頻電路按照以上說法可以寫爲
module half_clk(reset, clk_in, clk_out);
input reset, clk_in;
output clk_out;
reg clk_out;
reg[2:0] cnt;
always @(posedge clk_in or negedge clk_in)
begin
if(!reset)
begin
cnt <= 3'b000;
clk_out <= 0;
end
else
if(cnt==5)
begin
cnt<=3'b000;
clk_out <= ~clk_out;
end
else cnt <= cnt+1;
end
endmodule
也有另一種寫法:
module half_clk(reset, clk_in, clk_out);
input reset, clk_in;
output clk_out;
reg clk_out;
reg[1:0] cnt;
always @(posedge clk_in) //沒有下降沿觸發
begin
if(!reset)
begin
cnt <= 2'b00;
clk_out <= 0;
end
else
if(cnt==2)
begin
cnt<=2'b00;
clk_out <= ~clk_out;
end
else cnt <= cnt+1;
end
endmodule
還有一些2的冪次方的分頻器,有更簡單的寫法:
module half_clk(reset, clk_in, clk_out2, clk_out4, clk_out8, clk_out16);
input reset, clk_in;
output clk_out2,clk_out4,clk_out8,clk_out16;
wire clk_out2,clk_out4,clk_out8,clk_out16;
reg[3:0] cnt;
always @(posedge clk_in)
begin
if(!reset)
begin
cnt <= 4'b0000;
end
else cnt <= cnt + 1;
end
assign {clk_out16, clk_out8, clk_out4, clk_out2}=cnt;
endmodule
在硬件設計時,還經常遇到要求佔空比不是1:1的分頻信號,如下面佔空比1:7的分頻電路:
module half_clk(reset, clk_in,clk_out);
input reset, clk_in;
output clk_out;
reg clk_out;
reg[2:0] cnt;
always @(posedge clk_in)
if(!reset)
cnt <= 3'b000;
else cnt <= cnt + 1;
always @(posedge clk_in)
begin
if(!reset) clk_out <= 0;
else
if(cnt==3'b111)
clk_out <= 1;
else
clk_out <= 0;
end
endmodule