SV——Verilog和System Verilog中字面值表示

 

0. 介紹

字面值（literal integer）就是類似5、'h10這種值。

 

1. syntax

<size>'s<base><value>

• <size> is optional. If given, it specifies the total number of bits represented by the literal integer. If not given, the default size, per the Verilog/SystemVerilog standard is "at least"32 bits.
• s is optional. If given, it specifies thatthe literal integer should be treated as a signed value in operations. If not given, the default is unsigned. (The signed specifier wasadded to Verilog as part of the Verilog-200I standard.)
• <base> is required, and specifies whether the value is in binary, octal, decimal, or hex.
• <value> is required, andspecifies the literal integer value.

The baseoptions are represented using b, 0, d, or h for binary, octal, decimal andhex,
respectively. The base specifier can be either lowercase or uppercase (i.e. ' h 5
and ' H5 are the same).

2. 符號

Unbased literal integers default to signed. Based literal integers default to unsigned.

比如5，表示有符號的5；'d5表示無符號5.

3. 例子

byte in; // signed a-bit variables
int outl, out2; // signed 32~bit variables
initial begin
    in ==-5;
    out1 = in + 1; //  OK: -5 + 1 = -4 (literal 1 is signed)
    out2 = in + 1'b1; // GOTCHA: -5 +1'b1 = 252 (1'b1 is unsigned)
end

•  負數的運算先轉化成補碼，補碼計算之後再轉換成原碼。

    負數補碼=（符號位不變）其他位按位取反+1；

    負數原碼=（符號位不變）-1之後，按位取反；

    正數補碼=原碼；

    所以out1 = in+1=(11111011)補 + （1）補 = （11111100）補 = （10000100）原 = -4（十進制）

• 負數和正數運算

    負數會被當做正數，即負數in的補碼（11111011）被當做正的251，所以out2爲252.

 

3. reference

《Verilog and SystemVerilog Gotchas》