Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Fri Dec 21 18:23:40 2012
Command Line: D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
-o
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/ISE/Led-B/pr_verify.log
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd
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H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd: Fri Dec 21 17:42:54 2012
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd: Fri Dec 21 18:22:33 2012
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H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd: Fri Dec 21 18:22:32 2012
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd
Number of matched proxy logic bels = 82
Number of matched external nets = 80
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0
Verification completed successfully!
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd
ERROR:HDTools:30 - Found different numbers of proxy logic - 82/74.
Number of matched proxy logic bels = 0
Number of matched external nets = 0
Number of matched global clock nets = 0
Number of matched Reconfigurable Partitions = 0
VERIFICATION FAILED!
Verification completed with Errors.
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd
ERROR:HDTools:30 - Found different numbers of proxy logic - 74/82.
Number of matched proxy logic bels = 0
Number of matched external nets = 0
Number of matched global clock nets = 0
Number of matched Reconfigurable Partitions = 0
VERIFICATION FAILED!
Verification completed with Errors.
D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_b/led_b_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Try1/PlanAhead_
Try1.runs/black_box/black_box_routed.ncd => FAIL