PR3
Release 14.2 - pr_verify P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Sat Dec 22 11:18:53 2012
Command Line: D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
-o
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/ISE/Led-B/pr_verify.log
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd: Sat Dec 22 11:05:54 2012
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd: Sat Dec 22 11:16:37 2012
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd: Sat Dec 22 11:16:55 2012
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
ERROR:HDTools:54 - Static logic is inconsistent between configurations
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_bb/led_bb_routed.ncd" and
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_a/led_a_routed.ncd". Static logic must have an
identical implementation in all configurations.
ERROR:HDTools:7 - Constant network summary:
Matched trees: 212
Unmatched trees: 1
ERROR:HDTools:32 - Found routing differences.
Number of matched proxy logic bels = 74
Number of matched external nets = 71
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0
VERIFICATION FAILED!
Verification completed with Errors.
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd
Number of matched proxy logic bels = 74
Number of matched external nets = 72
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0
Verification completed successfully!
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
ERROR:HDTools:54 - Static logic is inconsistent between configurations
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_b/led_b_routed.ncd" and
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_bb/led_bb_routed.ncd". Static logic must have an
identical implementation in all configurations.
ERROR:HDTools:7 - Constant network summary:
Matched trees: 212
Unmatched trees: 10
ERROR:HDTools:7 - Constant network summary:
Matched trees: 211
Unmatched trees: 1
ERROR:HDTools:32 - Found routing differences.
Number of matched proxy logic bels = 74
Number of matched external nets = 70
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0
VERIFICATION FAILED!
Verification completed with Errors.
D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd => FAIL
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Sat Dec 22 11:18:53 2012
Command Line: D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
-o
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/ISE/Led-B/pr_verify.log
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd: Sat Dec 22 11:05:54 2012
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd: Sat Dec 22 11:16:37 2012
Loading
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd: Sat Dec 22 11:16:55 2012
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
ERROR:HDTools:54 - Static logic is inconsistent between configurations
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_bb/led_bb_routed.ncd" and
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_a/led_a_routed.ncd". Static logic must have an
identical implementation in all configurations.
ERROR:HDTools:7 - Constant network summary:
Matched trees: 212
Unmatched trees: 1
ERROR:HDTools:32 - Found routing differences.
Number of matched proxy logic bels = 74
Number of matched external nets = 71
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0
VERIFICATION FAILED!
Verification completed with Errors.
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd
Number of matched proxy logic bels = 74
Number of matched external nets = 72
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0
Verification completed successfully!
----------------------------------------
Analyzing Designs:
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
ERROR:HDTools:54 - Static logic is inconsistent between configurations
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_b/led_b_routed.ncd" and
"H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/Plan
Ahead_Import.runs/led_bb/led_bb_routed.ncd". Static logic must have an
identical implementation in all configurations.
ERROR:HDTools:7 - Constant network summary:
Matched trees: 212
Unmatched trees: 10
ERROR:HDTools:7 - Constant network summary:
Matched trees: 211
Unmatched trees: 1
ERROR:HDTools:32 - Found routing differences.
Number of matched proxy logic bels = 74
Number of matched external nets = 70
Number of matched global clock nets = 5
Number of matched Reconfigurable Partitions = 0
VERIFICATION FAILED!
Verification completed with Errors.
D:\Soft\ISE_14.X\14.2\ISE_DS\ISE\bin\nt\unwrapped\pr_verify.exe
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_bb/led_bb_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_a/led_a_routed.ncd
H:/FPGA/Xilinx/Zed-Board/ZedBoard-PartialReconfig-Demo/PlanAhead_Import/PlanAhea
d_Import.runs/led_b/led_b_routed.ncd => FAIL
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