1、GT基礎知識
SATA 接口只有幾根線爲什麼那麼快?連上網線顯示的10Gbps(萬兆網)是不是很令人興奮!沒錯,他們都用了高速GTX技術、GTX全稱Gigabit transceiver,是爲了滿足高速、實時傳輸而生的技術。傳統的並行傳輸技術存在抗干擾能力低,同步能力差,傳輸速度低和信號質量差等問題。GTX目前的線速度範圍是1Gbps - 12Gbps,有效負載範圍0.8Gbps - 10Gbps。目前GTX已經應用於光纖通道(FC),PCIE,Rapid io,串行SATA ,千兆以太網,萬兆以太網等。
GTX收發器採用的是差分信號對數據進行傳輸,其中LVDS(Low voltage different signal )和CML(current mode logic)是常用的兩種差分信號標準。差分信號因爲線路上收到的噪聲干擾幾乎完全相同,在計算差值相減從而達到抵消的效果,這就使得差分信號抗干擾能力特別強,高速傳輸時不易出錯。
除了差分信號外,GTX採用自同步技術來解決時鐘問題。目前常用的同步方式有:系統同步、源同步、自同步。系統同步利用片外的晶振進行同步,由於板間線路的長度不一致,以及片內延遲不一致,在時鐘速到提高時可能存在較大誤差。源同步是在發送數據同時發送一個時鐘副本,這種設計需要更多的時鐘端口。自同步講時鐘包含在數據流中,從數據流中恢復時鐘,不僅端口使用較少,而且不論是高速還是低速,時鐘延遲和數據延遲都是一樣的,可以保證採樣的正確性。
自同步接口主要包含三個模塊分別是並串轉換、串並轉換和時鐘恢復。時鐘恢復是利用鎖相環(PLL)合成出一個與輸入串行信號的時鐘頻率一致的時鐘,供採集數據用。
GTX包含兩大部分,PMA PCS。
PMA(物理媒介附加子層)主要功能是 : 串並\並串轉換和模擬部分。提供高性能的串行接口,如預加重、均衡。
PCS(物理編碼子層)主要是並行數字電路處理。數字流的編碼/解碼,8B\10B等。
2 GTX速度到底可以跑到多少
關於器件速度的問題首先找到 ds182->Kintex-7 FPGAs Data Sheet:DC and AC Switching Characteristics,可以自己對應的器件去找,不過這個在設計電路板器件選型的時候就應該考慮到,除非是買的開發部學習用。這裏麪包括所有的FPGA各個器件能跑到的最高頻率和器件延時,建立時間,保持時間等,對高速設計有很大的參考價值。找到GTX Transceiver Switching Characteristics
可以看到,雖然K7系列GTX最高可以跑到12.5Gbps,但這跟速度等級和封裝都有關係,是在-3的速度等級,FF封裝下才有的最高速度12.5Gbps。而現在手頭的芯片型號是K7480TFFG901-1,所以最高支持8.0Gbps。其實這在配置IP核的時候就會發現了,線速範圍是(0.5-8.0)。所以IP核都是嚴格和工程的器件相關聯的,這點Vivado越做越好了。
另外,速度還和CPLL QPLL 有關,以前一直以爲CPLL 和QPLL 的區別就是在用時鐘共享的時候會有區別。
3. GTX 硬件結構
下面圖均以325T爲例
當整個芯片多個GTX被使用時,需要合理的分佈GTX與時鐘輸入。從一個Quad輸入的時鐘往上只能給相鄰的一個Quad提供時鐘,往下也只能給相鄰的一個Quad提供時鐘輸入,最多隻能驅動三個Quad,當整個芯片多個GTX使用到同樣的參考時鐘輸入時,合理的分佈時鐘輸入可以節省需要的時鐘數量,併爲時鐘的提供冗餘設計。因此,基本的原則是同一個物理接口的幾個GTX放在一起,由同一個參考時鐘作爲時鐘輸入;不同物理接口的GTX如果在同一個參考時鐘的驅動覆蓋範圍內,可以採用同一個參考時鐘輸入。有條件的情況下,可以做時鐘備份;當一個時鐘可以覆蓋更多個GTX的時候,考慮到時鐘驅動能力的不確定性,爲留有更多餘量,沒必要使用到極限(一個時鐘驅動12個GTX)(比如我在調試aurora的時候,一個參考時鐘輸入,驅動3個bank,理論上是沒問題的,但是編譯時報錯。報錯原因不是一個qpll不能驅動3個bank,而是上圖中每個qpll都包含了一個common,這個common模塊是不能共享的。aurora在使用爲從核模式,共享邏輯在example下,自動的屏蔽掉了common邏輯,導致其他兩個bank的qpll裏面沒有common。修改IP 源碼,把common模塊添加到QPLL裏,問題得到解決。其實,最好的辦法是,每個bank都預留一個參考時鐘)。另外在V5的GTP中,關於多個GTP共用同一個參考時鐘輸入,要求在這個輸入時鐘的時鐘鏈上,每一個GTP都被使用(即使不需要,也要例化),不允許共用同一個參考時鐘的兩個GTP中間有一個沒有使用的GTP
GTX整體功能結構
4. 7 Series FPGAs TransceiversWizard IP 核介紹
1)選擇shared logic選項,最好選include shared logic in example design
2)
-------------------------------------- 下面摘自其他文章,內部參數和上圖不匹配,解析具有參考價值-----------------
先是協議,最簡單的strat from cratch,就是沒有協議。然後是線速,可以看到範圍是(0.5-8.0)。參考時鐘,這個可以根據需要選個合適的。軟件都根據你的線速把參考時鐘的可選項計算好了。接收端同樣設置,當然可以不一樣的。這是全雙工,收發鏈路沒有什麼關係,也可以關掉其中一個Tx off 或Rx off。然後是PLL選擇,到底選哪個呢?根據時鐘頻率選擇
然後是比較重要的,選擇用哪個收發器,這當然不是拍腦袋決定的,跟設計有關,可以查找原理圖
比如說這樣的,然後去查手冊UG476-> 7 Series FPGAsGTX/GTH Transceivers 找到 Placement Information by Package如下
這樣就知道用的是X0Y8,輸入時鐘在上面的原理圖可以找到,是同一組的clk0。
3)
4)
5)
可選端口其實有的挺有用的,增加了可控性,比如說環回控制,LOOPBACK。順便說一下內部環回有四種,
1.“000”:正常模式不環回
2.“001”:近端PCS環回
3.“010”:近端PMA環回
4.“100”:遠端PMA環回
5.“110”:遠端PCS環回)
6)
接下來是通道綁定和時鐘校正。通道綁定的作用是把多個物理通道對齊,綁定成一個的邏輯通道。其實就是用FIFO消除通道間的延時不確定性。由於只有一個通道,沒有綁定可言。
7)檢查一下對不對
5. 調用例程
gtwizard_0 u_gtwizard_0
(
.soft_reset_tx_in(rst | reg_gtp_rst[0]),
.soft_reset_rx_in(rst | reg_gtp_rst[1]),
.dont_reset_on_data_error_in(1'b0),
.q0_clk1_gtrefclk_pad_n_in(gtp_refclk_n),
.q0_clk1_gtrefclk_pad_p_in(gtp_refclk_p),
.gt0_tx_mmcm_lock_out( ),
.gt0_rx_mmcm_lock_out( ),
.gt0_tx_fsm_reset_done_out( ),
.gt0_rx_fsm_reset_done_out( ),
.gt0_data_valid_in(1'b1),
.gt1_tx_mmcm_lock_out( ),
.gt1_rx_mmcm_lock_out( ),
.gt1_tx_fsm_reset_done_out( ),
.gt1_rx_fsm_reset_done_out( ),
.gt1_data_valid_in(1'b1),
.gt2_tx_mmcm_lock_out( ),
.gt2_rx_mmcm_lock_out( ),
.gt2_tx_fsm_reset_done_out( ),
.gt2_rx_fsm_reset_done_out( ),
.gt2_data_valid_in(1'b1),
.gt3_tx_mmcm_lock_out( ),
.gt3_rx_mmcm_lock_out( ),
.gt3_tx_fsm_reset_done_out( ),
.gt3_rx_fsm_reset_done_out(gt3_rx_fsm_reset_done_out),
.gt3_data_valid_in(1'b1),
.gt0_txusrclk_out( ),
.gt0_txusrclk2_out(gt0_txusrclk_out),
.gt0_rxusrclk_out( ),
.gt0_rxusrclk2_out(gt0_rxusrclk_out),
.gt1_txusrclk_out( ),
.gt1_txusrclk2_out(gt1_txusrclk_out),
.gt1_rxusrclk_out( ),
.gt1_rxusrclk2_out(gt1_rxusrclk_out),
.gt2_txusrclk_out( ),
.gt2_txusrclk2_out(gt2_txusrclk_out),
.gt2_rxusrclk_out( ),
.gt2_rxusrclk2_out(gt2_rxusrclk_out),
.gt3_txusrclk_out( ),
.gt3_txusrclk2_out(gt3_txusrclk_out),
.gt3_rxusrclk_out( ),
.gt3_rxusrclk2_out(gt3_rxusrclk_out),
//_________________________________________________________________________
//GT0 (X0Y0)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
.gt0_cpllfbclklost_out ( ), // output wire gt0_cpllfbclklost_out
.gt0_cplllock_out ( ), // output wire gt0_cplllock_out
.gt0_cpllreset_in (1'b0), // input wire gt0_cpllreset_in
//-------------------------- Channel - DRP Ports --------------------------
.gt0_drpaddr_in (9'd0), // input wire [8:0] gt0_drpaddr_in
.gt0_drpdi_in (16'd0), // input wire [15:0] gt0_drpdi_in
.gt0_drpdo_out ( ), // output wire [15:0] gt0_drpdo_out
.gt0_drpen_in (1'b0), // input wire gt0_drpen_in
.gt0_drprdy_out ( ), // output wire gt0_drprdy_out
.gt0_drpwe_in (1'b0), // input wire gt0_drpwe_in
//------------------------- Digital Monitor Ports --------------------------
.gt0_dmonitorout_out ( ), // output wire [7:0] gt0_dmonitorout_out
//----------------------------- Loopback Ports -----------------------------
.gt0_loopback_in (3'd0), // input wire [2:0] gt0_loopback_in
//------------------- RX Initialization and Reset Ports --------------------
.gt0_eyescanreset_in (1'b0), // input wire gt0_eyescanreset_in
.gt0_rxuserrdy_in (1'b1), // input wire gt0_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
.gt0_eyescandataerror_out ( ), // output wire gt0_eyescandataerror_out
.gt0_eyescantrigger_in (1'b0), // input wire gt0_eyescantrigger_in
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.gt0_rxdata_out (gt0_rxdata_out), // output wire [31:0] gt0_rxdata_out
//----------------- Receive Ports - Pattern Checker Ports ------------------
.gt0_rxprbserr_out (gt0_rxprbserr_out), // output wire gt0_rxprbserr_out
.gt0_rxprbssel_in (3'b0), // input wire [2:0] gt0_rxprbssel_in
//----------------- Receive Ports - Pattern Checker ports ------------------
.gt0_rxprbscntreset_in (1'b0), // input wire gt0_rxprbscntreset_in
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.gt0_rxdisperr_out (gt0_rxdisperr_out), // output wire [3:0] gt0_rxdisperr_out
.gt0_rxnotintable_out (gt0_rxnotintable_out), // output wire [3:0] gt0_rxnotintable_out
//------------------------- Receive Ports - RX AFE -------------------------
.gt0_gtxrxp_in (rx_serdout0_p), // input wire gt0_gtxrxp_in
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt0_gtxrxn_in (rx_serdout0_n), // input wire gt0_gtxrxn_in
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.gt0_rxbufstatus_out ( ), // output wire [2:0] gt0_rxbufstatus_out
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.gt0_rxbyterealign_out ( ), // output wire gt0_rxbyterealign_out
.gt0_rxmcommaalignen_in (gt0_rxmcommaalignen_in), // input wire gt0_rxmcommaalignen_in
.gt0_rxpcommaalignen_in (gt0_rxmcommaalignen_in), // input wire gt0_rxpcommaalignen_in
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt0_rxdfelpmreset_in (1'b0), // input wire gt0_rxdfelpmreset_in
.gt0_rxmonitorout_out ( ), // output wire [6:0] gt0_rxmonitorout_out
.gt0_rxmonitorsel_in (2'b0), // input wire [1:0] gt0_rxmonitorsel_in
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt0_rxoutclkfabric_out ( ), // output wire gt0_rxoutclkfabric_out
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt0_gtrxreset_in (1'b0), // input wire gt0_gtrxreset_in
.gt0_rxpmareset_in (1'b0), // input wire gt0_rxpmareset_in
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.gt0_rxchariscomma_out ( ), // output wire [3:0] gt0_rxchariscomma_out
.gt0_rxcharisk_out (gt0_rxcharisk_out), // output wire [3:0] gt0_rxcharisk_out
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt0_rxresetdone_out (gt0_rxresetdone_out), // output wire gt0_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt0_gttxreset_in (1'b0), // input wire gt0_gttxreset_in
.gt0_txuserrdy_in (1'b0), // input wire gt0_txuserrdy_in
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.gt0_txbufstatus_out ( ), // output wire [1:0] gt0_txbufstatus_out
//---------------- Transmit Ports - TX Data Path interface -----------------
.gt0_txdata_in (gt0_txdata_in), // input wire [31:0] gt0_txdata_in
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt0_gtxtxn_out (tx_serdin0_n), // output wire gt0_gtxtxn_out
.gt0_gtxtxp_out (tx_serdin0_p), // output wire gt0_gtxtxp_out
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.gt0_txoutclkfabric_out ( ), // output wire gt0_txoutclkfabric_out
.gt0_txoutclkpcs_out ( ), // output wire gt0_txoutclkpcs_out
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.gt0_txcharisk_in (gt0_txcharisk_in), // input wire [3:0] gt0_txcharisk_in
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt0_txresetdone_out (gt0_txresetdone_out), // output wire gt0_txresetdone_out
//---------------- Transmit Ports - pattern Generator Ports ----------------
.gt0_txprbssel_in (3'b0), // input wire [2:0] gt0_txprbssel_in
//GT1 (X0Y1)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
.gt1_cpllfbclklost_out ( ), // output wire gt1_cpllfbclklost_out
.gt1_cplllock_out ( ), // output wire gt1_cplllock_out
.gt1_cpllreset_in (1'b0), // input wire gt1_cpllreset_in
//-------------------------- Channel - DRP Ports --------------------------
.gt1_drpaddr_in (9'd0), // input wire [8:0] gt1_drpaddr_in
.gt1_drpdi_in (16'd0), // input wire [15:0] gt1_drpdi_in
.gt1_drpdo_out ( ), // output wire [15:0] gt1_drpdo_out
.gt1_drpen_in (1'b0), // input wire gt1_drpen_in
.gt1_drprdy_out ( ), // output wire gt1_drprdy_out
.gt1_drpwe_in (1'b0), // input wire gt1_drpwe_in
//------------------------- Digital Monitor Ports --------------------------
.gt1_dmonitorout_out ( ), // output wire [7:0] gt1_dmonitorout_out
//----------------------------- Loopback Ports -----------------------------
.gt1_loopback_in (3'd0), // input wire [2:0] gt1_loopback_in
//------------------- RX Initialization and Reset Ports --------------------
.gt1_eyescanreset_in (1'b0), // input wire gt1_eyescanreset_in
.gt1_rxuserrdy_in (1'b1), // input wire gt1_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
.gt1_eyescandataerror_out ( ), // output wire gt1_eyescandataerror_out
.gt1_eyescantrigger_in (1'b0), // input wire gt1_eyescantrigger_in
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.gt1_rxdata_out (gt1_rxdata_out), // output wire [31:0] gt1_rxdata_out
//----------------- Receive Ports - Pattern Checker Ports ------------------
.gt1_rxprbserr_out (gt1_rxprbserr_out), // output wire gt1_rxprbserr_out
.gt1_rxprbssel_in (3'b0), // input wire [2:0] gt1_rxprbssel_in
//----------------- Receive Ports - Pattern Checker ports ------------------
.gt1_rxprbscntreset_in (1'b0), // input wire gt1_rxprbscntreset_in
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.gt1_rxdisperr_out (gt1_rxdisperr_out), // output wire [3:0] gt1_rxdisperr_out
.gt1_rxnotintable_out (gt1_rxnotintable_out), // output wire [3:0] gt1_rxnotintable_out
//------------------------- Receive Ports - RX AFE -------------------------
.gt1_gtxrxp_in (rx_serdout1_p), // input wire gt1_gtxrxp_in
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt1_gtxrxn_in (rx_serdout1_n), // input wire gt1_gtxrxn_in
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.gt1_rxbufstatus_out ( ), // output wire [2:0] gt1_rxbufstatus_out
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.gt1_rxbyterealign_out ( ), // output wire gt1_rxbyterealign_out
.gt1_rxmcommaalignen_in (gt0_rxmcommaalignen_in), // input wire gt1_rxmcommaalignen_in
.gt1_rxpcommaalignen_in (gt0_rxmcommaalignen_in), // input wire gt1_rxpcommaalignen_in
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt1_rxdfelpmreset_in (1'b0), // input wire gt1_rxdfelpmreset_in
.gt1_rxmonitorout_out ( ), // output wire [6:0] gt1_rxmonitorout_out
.gt1_rxmonitorsel_in (2'b0), // input wire [1:0] gt1_rxmonitorsel_in
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt1_rxoutclkfabric_out ( ), // output wire gt1_rxoutclkfabric_out
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt1_gtrxreset_in (1'b0), // input wire gt1_gtrxreset_in
.gt1_rxpmareset_in (1'b0), // input wire gt1_rxpmareset_in
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.gt1_rxchariscomma_out ( ), // output wire [3:0] gt1_rxchariscomma_out
.gt1_rxcharisk_out (gt1_rxcharisk_out), // output wire [3:0] gt1_rxcharisk_out
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt1_rxresetdone_out (gt1_rxresetdone_out), // output wire gt1_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt1_gttxreset_in (1'b0), // input wire gt1_gttxreset_in
.gt1_txuserrdy_in (1'b0), // input wire gt1_txuserrdy_in
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.gt1_txbufstatus_out ( ), // output wire [1:0] gt1_txbufstatus_out
//---------------- Transmit Ports - TX Data Path interface -----------------
.gt1_txdata_in (gt1_txdata_in), // input wire [31:0] gt1_txdata_in
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt1_gtxtxn_out (tx_serdin1_n), // output wire gt1_gtxtxn_out
.gt1_gtxtxp_out (tx_serdin1_p), // output wire gt1_gtxtxp_out
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.gt1_txoutclkfabric_out ( ), // output wire gt1_txoutclkfabric_out
.gt1_txoutclkpcs_out ( ), // output wire gt1_txoutclkpcs_out
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.gt1_txcharisk_in (gt1_txcharisk_in), // input wire [3:0] gt1_txcharisk_in
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt1_txresetdone_out (gt1_txresetdone_out), // output wire gt1_txresetdone_out
//---------------- Transmit Ports - pattern Generator Ports ----------------
.gt1_txprbssel_in (3'b0), // input wire [2:0] gt1_txprbssel_in
//GT2 (X0Y2)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
.gt2_cpllfbclklost_out ( ), // output wire gt2_cpllfbclklost_out
.gt2_cplllock_out ( ), // output wire gt2_cplllock_out
.gt2_cpllreset_in (1'b0), // input wire gt2_cpllreset_in
//-------------------------- Channel - DRP Ports --------------------------
.gt2_drpaddr_in (9'd0), // input wire [8:0] gt2_drpaddr_in
.gt2_drpdi_in (16'd0), // input wire [15:0] gt2_drpdi_in
.gt2_drpdo_out ( ), // output wire [15:0] gt2_drpdo_out
.gt2_drpen_in (1'b0), // input wire gt2_drpen_in
.gt2_drprdy_out ( ), // output wire gt2_drprdy_out
.gt2_drpwe_in (1'b0), // input wire gt2_drpwe_in
//------------------------- Digital Monitor Ports --------------------------
.gt2_dmonitorout_out ( ), // output wire [7:0] gt2_dmonitorout_out
//----------------------------- Loopback Ports -----------------------------
.gt2_loopback_in (3'd0), // input wire [2:0] gt2_loopback_in
//------------------- RX Initialization and Reset Ports --------------------
.gt2_eyescanreset_in (1'b0), // input wire gt2_eyescanreset_in
.gt2_rxuserrdy_in (1'b1), // input wire gt2_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
.gt2_eyescandataerror_out ( ), // output wire gt2_eyescandataerror_out
.gt2_eyescantrigger_in (1'b0), // input wire gt2_eyescantrigger_in
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.gt2_rxdata_out (gt2_rxdata_out), // output wire [31:0] gt2_rxdata_out
//----------------- Receive Ports - Pattern Checker Ports ------------------
.gt2_rxprbserr_out (gt2_rxprbserr_out), // output wire gt2_rxprbserr_out
.gt2_rxprbssel_in (3'b0), // input wire [2:0] gt2_rxprbssel_in
//----------------- Receive Ports - Pattern Checker ports ------------------
.gt2_rxprbscntreset_in (1'b0), // input wire gt2_rxprbscntreset_in
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.gt2_rxdisperr_out (gt2_rxdisperr_out), // output wire [3:0] gt2_rxdisperr_out
.gt2_rxnotintable_out (gt2_rxnotintable_out), // output wire [3:0] gt2_rxnotintable_out
//------------------------- Receive Ports - RX AFE -------------------------
.gt2_gtxrxp_in (fb_serdout0_p), // input wire gt2_gtxrxp_in
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt2_gtxrxn_in (fb_serdout0_n), // input wire gt2_gtxrxn_in
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.gt2_rxbufstatus_out ( ), // output wire [2:0] gt2_rxbufstatus_out
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.gt2_rxbyterealign_out ( ), // output wire gt2_rxbyterealign_out
.gt2_rxmcommaalignen_in (gt2_rxmcommaalignen_in), // input wire gt2_rxmcommaalignen_in
.gt2_rxpcommaalignen_in (gt2_rxmcommaalignen_in), // input wire gt2_rxpcommaalignen_in
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt2_rxdfelpmreset_in (1'b0), // input wire gt2_rxdfelpmreset_in
.gt2_rxmonitorout_out ( ), // output wire [6:0] gt2_rxmonitorout_out
.gt2_rxmonitorsel_in (2'b0), // input wire [1:0] gt2_rxmonitorsel_in
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt2_rxoutclkfabric_out ( ), // output wire gt2_rxoutclkfabric_out
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt2_gtrxreset_in (1'b0), // input wire gt2_gtrxreset_in
.gt2_rxpmareset_in (1'b0), // input wire gt2_rxpmareset_in
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.gt2_rxchariscomma_out ( ), // output wire [3:0] gt2_rxchariscomma_out
.gt2_rxcharisk_out (gt2_rxcharisk_out), // output wire [3:0] gt2_rxcharisk_out
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt2_rxresetdone_out (gt2_rxresetdone_out), // output wire gt2_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt2_gttxreset_in (1'b0), // input wire gt2_gttxreset_in
.gt2_txuserrdy_in (1'b0), // input wire gt2_txuserrdy_in
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.gt2_txbufstatus_out ( ), // output wire [1:0] gt2_txbufstatus_out
//---------------- Transmit Ports - TX Data Path interface -----------------
.gt2_txdata_in (gt2_txdata_in), // input wire [31:0] gt2_txdata_in
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt2_gtxtxn_out (tx_serdin2_n), // output wire gt2_gtxtxn_out
.gt2_gtxtxp_out (tx_serdin2_p), // output wire gt2_gtxtxp_out
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.gt2_txoutclkfabric_out ( ), // output wire gt2_txoutclkfabric_out
.gt2_txoutclkpcs_out ( ), // output wire gt2_txoutclkpcs_out
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.gt2_txcharisk_in (gt2_txcharisk_in), // input wire [3:0] gt2_txcharisk_in
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt2_txresetdone_out (gt2_txresetdone_out), // output wire gt2_txresetdone_out
//---------------- Transmit Ports - pattern Generator Ports ----------------
.gt2_txprbssel_in (3'b0), // input wire [2:0] gt2_txprbssel_in
//GT3 (X0Y3)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
.gt3_cpllfbclklost_out ( ), // output wire gt3_cpllfbclklost_out
.gt3_cplllock_out ( ), // output wire gt3_cplllock_out
.gt3_cpllreset_in (1'b0), // input wire gt3_cpllreset_in
//-------------------------- Channel - DRP Ports --------------------------
.gt3_drpaddr_in (9'd0), // input wire [8:0] gt3_drpaddr_in
.gt3_drpdi_in (16'd0), // input wire [15:0] gt3_drpdi_in
.gt3_drpdo_out ( ), // output wire [15:0] gt3_drpdo_out
.gt3_drpen_in (1'b0), // input wire gt3_drpen_in
.gt3_drprdy_out ( ), // output wire gt3_drprdy_out
.gt3_drpwe_in (1'b0), // input wire gt3_drpwe_in
//------------------------- Digital Monitor Ports --------------------------
.gt3_dmonitorout_out ( ), // output wire [7:0] gt3_dmonitorout_out
//----------------------------- Loopback Ports -----------------------------
.gt3_loopback_in (3'd0), // input wire [2:0] gt3_loopback_in
//------------------- RX Initialization and Reset Ports --------------------
.gt3_eyescanreset_in (1'b0), // input wire gt3_eyescanreset_in
.gt3_rxuserrdy_in (1'b1), // input wire gt3_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
.gt3_eyescandataerror_out ( ), // output wire gt3_eyescandataerror_out
.gt3_eyescantrigger_in (1'b0), // input wire gt3_eyescantrigger_in
//---------------- Receive Ports - FPGA RX interface Ports -----------------
.gt3_rxdata_out (gt3_rxdata_out), // output wire [31:0] gt3_rxdata_out
//----------------- Receive Ports - Pattern Checker Ports ------------------
.gt3_rxprbserr_out (gt3_rxprbserr_out), // output wire gt3_rxprbserr_out
.gt3_rxprbssel_in (3'b0), // input wire [2:0] gt3_rxprbssel_in
//----------------- Receive Ports - Pattern Checker ports ------------------
.gt3_rxprbscntreset_in (1'b0), // input wire gt3_rxprbscntreset_in
//---------------- Receive Ports - RX 8B/10B Decoder Ports -----------------
.gt3_rxdisperr_out (gt3_rxdisperr_out), // output wire [3:0] gt3_rxdisperr_out
.gt3_rxnotintable_out (gt3_rxnotintable_out), // output wire [3:0] gt3_rxnotintable_out
//------------------------- Receive Ports - RX AFE -------------------------
.gt3_gtxrxp_in (fb_serdout1_p), // input wire gt3_gtxrxp_in
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt3_gtxrxn_in (fb_serdout1_n), // input wire gt3_gtxrxn_in
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
.gt3_rxbufstatus_out ( ), // output wire [2:0] gt3_rxbufstatus_out
//------------ Receive Ports - RX Byte and Word Alignment Ports ------------
.gt3_rxbyterealign_out ( ), // output wire gt3_rxbyterealign_out
.gt3_rxmcommaalignen_in (gt3_rxmcommaalignen_in), // input wire gt3_rxmcommaalignen_in
.gt3_rxpcommaalignen_in (gt3_rxmcommaalignen_in), // input wire gt3_rxpcommaalignen_in
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt3_rxdfelpmreset_in (1'b0), // input wire gt3_rxdfelpmreset_in
.gt3_rxmonitorout_out ( ), // output wire [6:0] gt3_rxmonitorout_out
.gt3_rxmonitorsel_in (2'b0), // input wire [1:0] gt3_rxmonitorsel_in
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt3_rxoutclkfabric_out ( ), // output wire gt3_rxoutclkfabric_out
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt3_gtrxreset_in (1'b0), // input wire gt3_gtrxreset_in
.gt3_rxpmareset_in (1'b0), // input wire gt3_rxpmareset_in
//----------------- Receive Ports - RX8B/10B Decoder Ports -----------------
.gt3_rxchariscomma_out ( ), // output wire [3:0] gt3_rxchariscomma_out
.gt3_rxcharisk_out (gt3_rxcharisk_out), // output wire [3:0] gt3_rxcharisk_out
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt3_rxresetdone_out (gt3_rxresetdone_out), // output wire gt3_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt3_gttxreset_in (1'b0), // input wire gt3_gttxreset_in
.gt3_txuserrdy_in (1'b0), // input wire gt3_txuserrdy_in
//-------------------- Transmit Ports - TX Buffer Ports --------------------
.gt3_txbufstatus_out ( ), // output wire [1:0] gt3_txbufstatus_out
//---------------- Transmit Ports - TX Data Path interface -----------------
.gt3_txdata_in (gt3_txdata_in), // input wire [31:0] gt3_txdata_in
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt3_gtxtxn_out (tx_serdin3_n), // output wire gt3_gtxtxn_out
.gt3_gtxtxp_out (tx_serdin3_p), // output wire gt3_gtxtxp_out
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.gt3_txoutclkfabric_out ( ), // output wire gt3_txoutclkfabric_out
.gt3_txoutclkpcs_out ( ), // output wire gt3_txoutclkpcs_out
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.gt3_txcharisk_in (gt3_txcharisk_in), // input wire [3:0] gt3_txcharisk_in
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt3_txresetdone_out (gt3_txresetdone_out), // output wire gt3_txresetdone_out
//---------------- Transmit Ports - pattern Generator Ports ----------------
.gt3_txprbssel_in (3'b0), // input wire [2:0] gt3_txprbssel_in
//____________________________COMMON PORTS________________________________
.gt0_qplloutclk_out(gt0_pll0outclk_out),
.gt0_qplloutrefclk_out(gt0_pll0outrefclk_out),
.sysclk_in(core_clk)
);
除了下圖藍色的,其他的不是全0 就是全1 。