Verilog 100MHZ時鐘 2分頻 3分頻

`timescale 1ns/1ns
module clock;
	reg clk; // initial clock
	reg clk_2;// 2 clk
	reg [1:0] count;
	reg clk_3;// posedge 3 clk 1/3
	reg clk_3_n;// negedge 3 clk 1/3
	reg [1:0] count2;
	reg clk_3_50;// 3 clk 1/2
	
	initial begin
		clk=0;
		clk_2=0;
		clk_3=0;
		count=0;
		clk_3_n=0;
		count2=0;
		clk_3_50=0;
	end
	always @ (*) begin
		clk_3_50 = clk_3 || clk_3_n;
	end
	always #5 clk=~clk;
	initial begin #1000 $stop; end
	always @ (posedge clk) begin
		clk_2=~clk_2;
	end
	always @ (posedge clk) begin //case() can be used here
		if (count==0) begin
			count=1; end
		else if (count==1) begin
			count=2;
			clk_3=~clk_3; end
		else begin
			count = 0;
			clk_3=~clk_3; end
	end
	always @ (negedge clk) begin //case() can be used here
		if (count==0) begin
			count2=1; end
		else if (count==1) begin
			count2=2;
			clk_3_n=~clk_3_n; end
		else begin
			count2= 0;
			clk_3_n=~clk_3_n; end
	end
endmodule