源碼:
module sel8_1(
a0,
a1,
a2,
a3,
a4,
a5,
a6,
a7,
b,
sel
);
input [3:0] a0,a1,a2,a3,a4,a5,a6,a7;
input [2:0] sel;
output [3:0] b;
reg [3:0] b;
// reg [3:0] c;
// c = 4'b1100;
//在always裏面的每一個信號都必須是reg
//reg信號也是不能在alway外的
always@(a0 or a1 or a2 or a3 or a4 or a5 or a6 or a7 or sel)
begin
case(sel)
3'b000: b = a0;
3'b001: b = a1;
3'b010: b = a2;
3'b011: b = a3;
3'b100: b = a4;
3'b101: b = a5;
3'b110: b = a6;
3'b111: b = a7;
default: b = 4'bx;
endcase
end
endmodule
測試代碼:
`timescale 1ns/1ns
module sel8_1tb;
reg [3:0] a0,a1,a2,a3,a4,a5,a6,a7;
reg [2:0] sel;
wire [3:0] b;
initial
begin
sel = 3'b0;
repeat(16)
begin
#5
sel = sel + 3'b1;
a0 = {$random}%16;
a1 = {$random}%16;
a2 = {$random}%16;
a3 = {$random}%16;
a4 = {$random}%16;
a5 = {$random}%16;
a6 = {$random}%16;
a7 = {$random}%16;
end
end
sel8_1 mysel8_1(
.a0(a0),
.a1(a1),
.a2(a2),
.a3(a3),
.a4(a4),
.a5(a5),
.a6(a6),
.a7(a7),
.b(b),
.sel(sel)
);//這種連接的工作,可以寫一個插件,如果有機會的話
endmodule
現象;