DAC——AD5060的使用

`timescale 1ns/1ns
`include "CLK_divide.v"

module AD5060(clk,rst,NL_SCLK,NL_SDIN,NL_SYNC);
    input clk,rst;
    output NL_SCLK;
    output reg NL_SDIN,NL_SYNC;
    
    reg [4:0]NLcount;
    reg NLflag;
    wire [23:0]NL_SDIN_ALL;
    assign NL_SDIN_ALL  = 24'b0000_0000_0011_1111_1111_1111;
    CLK_divide dvd1(clk,rst,NL_SCLK);
//按鍵消抖
reg [1:0] key_in_r;
wire pp;
reg [19:0] cnt_base;
reg key_value_r;
wire key_value;

//????
always @(posedge clk)
    key_in_r<=  {key_in_r[0],rst};

// ??????????
assign pp = key_in_r[0]^key_in_r[1]; 
//?????
always @(posedge clk)
    if(pp==1'b1)
       cnt_base <=  20'd0;
    else
       cnt_base <=  cnt_base + 1;

//??
always @(posedge clk)
   if(cnt_base==20'hf_ffff)
        key_value_r <=  key_in_r[0];

assign key_value = key_value_r;

    always @(negedge NL_SCLK or posedge key_value)           
    begin
        if(key_value) begin
            NL_SYNC <= 1; 
            NLcount <= 0; 
            NLflag  <= 0; 
            NL_SDIN <= 0;
        end
        else if(NLflag==0)begin  
            case(NLcount)
                    5'b00000: begin NL_SDIN = NL_SDIN_ALL[23] ; NLcount <= NLcount +1; NL_SYNC <= 0; end 
                    5'b00001: begin NL_SDIN = NL_SDIN_ALL[22] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00010: begin NL_SDIN = NL_SDIN_ALL[21] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00011: begin NL_SDIN = NL_SDIN_ALL[20] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00100: begin NL_SDIN = NL_SDIN_ALL[19] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00101: begin NL_SDIN = NL_SDIN_ALL[18] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00110: begin NL_SDIN = NL_SDIN_ALL[17] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00111: begin NL_SDIN = NL_SDIN_ALL[16] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01000: begin NL_SDIN = NL_SDIN_ALL[15] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01001: begin NL_SDIN = NL_SDIN_ALL[14] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01010: begin NL_SDIN = NL_SDIN_ALL[13] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01011: begin NL_SDIN = NL_SDIN_ALL[12] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01100: begin NL_SDIN = NL_SDIN_ALL[11] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01101: begin NL_SDIN = NL_SDIN_ALL[10] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01110: begin NL_SDIN = NL_SDIN_ALL[9]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01111: begin NL_SDIN = NL_SDIN_ALL[8]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end 
                    5'b10000: begin NL_SDIN = NL_SDIN_ALL[7]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10001: begin NL_SDIN = NL_SDIN_ALL[6]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10010: begin NL_SDIN = NL_SDIN_ALL[5]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10011: begin NL_SDIN = NL_SDIN_ALL[4]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10100: begin NL_SDIN = NL_SDIN_ALL[3]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10101: begin NL_SDIN = NL_SDIN_ALL[2]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10110: begin NL_SDIN = NL_SDIN_ALL[1]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end 
                    5'b10111: begin NL_SDIN = NL_SDIN_ALL[0]  ; NLcount <= 0;          NL_SYNC <= 0; NLflag<=1;end

                default: begin NL_SDIN = 0;                NLcount <= 0;          NL_SYNC <= 0; NLflag<=1; end
            endcase
        end
        else begin
            NL_SYNC <= 1; 
            NL_SDIN <= 0;
        end
    end
endmodule 

多次掃描

`timescale 1ns/1ns
`include "CLK_divide.v"

module AD5060(clk,rst,NL_SCLK,NL_SDIN,NL_SYNC);
    input clk,rst;
    output NL_SCLK;
    output reg NL_SDIN,NL_SYNC;
    
    reg [4:0]NLcount;
    reg [13:0]count;
    reg NLflag;
    reg [23:0]NL_SDIN_ALL;
//    wire [23:0]NL_SDIN_ALL2;
//    wire [23:0]NL_SDIN_ALL3;
    
 //   assign NL_SDIN_ALL  = 24'b0000_0000_0011_1111_1111_1111; //0000_0000_0000_0000; 1111_1111_1111_1111 0110_1010_1010_1010 0011_1111_1111_1111
//    assign NL_SDIN_ALL2  = 24'b0000_0000_0100_0111_0001_1100;   //0.5V
//    assign NL_SDIN_ALL3  = 24'b0000_0000_0110_1010_1010_1010;   //0.75V
    
    
    CLK_divide dvd1(clk,rst,NL_SCLK);
    
    reg [1:0] key_in_r;
wire pp;
reg [19:0] cnt_base;
reg key_value_r;
wire key_value;

//????
always @(posedge clk)
    key_in_r<=  {key_in_r[0],rst};

// ??????????
assign pp = key_in_r[0]^key_in_r[1]; 
//?????
always @(posedge clk)
    if(pp==1'b1)
       cnt_base <=  20'd0;
    else
       cnt_base <=  cnt_base + 1;

//??
always @(posedge clk)
   if(cnt_base==20'hf_ffff)
        key_value_r <=  key_in_r[0];

assign key_value = key_value_r;

    always @(negedge NL_SCLK or posedge key_value)           
    begin
        if(key_value) begin
            NL_SYNC <= 1; 
            NLcount <= 0; 
            count <= 0;
            NLflag  <= 0; 
            NL_SDIN <= 0;
            NL_SDIN_ALL  = 24'b0000_0000_0011_1111_1111_1111;
        end
        else if(NLflag==0)
            begin  
                case(NLcount)
                    5'b00000: begin NL_SDIN = NL_SDIN_ALL[23] ; NLcount <= NLcount +1; NL_SYNC <= 0; end 
                    5'b00001: begin NL_SDIN = NL_SDIN_ALL[22] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00010: begin NL_SDIN = NL_SDIN_ALL[21] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00011: begin NL_SDIN = NL_SDIN_ALL[20] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00100: begin NL_SDIN = NL_SDIN_ALL[19] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00101: begin NL_SDIN = NL_SDIN_ALL[18] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00110: begin NL_SDIN = NL_SDIN_ALL[17] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b00111: begin NL_SDIN = NL_SDIN_ALL[16] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01000: begin NL_SDIN = NL_SDIN_ALL[15] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01001: begin NL_SDIN = NL_SDIN_ALL[14] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01010: begin NL_SDIN = NL_SDIN_ALL[13] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01011: begin NL_SDIN = NL_SDIN_ALL[12] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01100: begin NL_SDIN = NL_SDIN_ALL[11] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01101: begin NL_SDIN = NL_SDIN_ALL[10] ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01110: begin NL_SDIN = NL_SDIN_ALL[9]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b01111: begin NL_SDIN = NL_SDIN_ALL[8]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end 
                    5'b10000: begin NL_SDIN = NL_SDIN_ALL[7]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10001: begin NL_SDIN = NL_SDIN_ALL[6]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10010: begin NL_SDIN = NL_SDIN_ALL[5]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10011: begin NL_SDIN = NL_SDIN_ALL[4]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10100: begin NL_SDIN = NL_SDIN_ALL[3]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10101: begin NL_SDIN = NL_SDIN_ALL[2]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end
                    5'b10110: begin NL_SDIN = NL_SDIN_ALL[1]  ; NLcount <= NLcount +1; NL_SYNC <= 0; end 
                    5'b10111: begin NL_SDIN = NL_SDIN_ALL[0]  ; NLcount <= 0;          NL_SYNC <= 0; NLflag<=1;end
                    
                    default: begin NL_SDIN = 0;                NLcount <= 0;          NL_SYNC <= 0; NLflag<=1; end
                endcase
            end

        else begin
            NL_SYNC <= 1;
            NL_SDIN <= 0;
            count <= count + 1;
            if(count == 2500)begin
//                count <= 0;
                NL_SDIN_ALL <= 24'b0000_0000_0100_0111_0001_1100;
                NLflag<=0;
            end
            else if(count ==5000)begin
                NL_SDIN_ALL <= 24'b0000_0000_0110_1010_1010_1010;
                NLflag<=0;
                count<=0;
            end
        end
    end
endmodule