ISE中进行综合后，查看生成的report，找到Timing Report部分。简要分析如下：
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATIONPLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
ClockSignal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk |BUFGP | 1699 |
coef/N0 | NONE(coef/BU308) |15 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were notautomatically buffered by XST with BUFG/BUFR resources. Please usethe buffer_type constraint in order to insert these buffers to theclock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------+----------------------------------+-------+
ControlSignal | Buffer(FFname) | Load |
---------------------------------------------------------+----------------------------------+-------+
coef/N0(coef/GND:G) |NONE(coef/BU11) | 60 |
fir/blk00000003/chan_in(0)(fir/blk00000003/blk00000004:G)|NONE(fir/blk00000003/blk00000a0f)| 24 |
reset_inv(reset_inv1_INV_0:O) |NONE(cnt_9) | 17 |
---------------------------------------------------------+----------------------------------+-------+
Timing Summary:
---------------
Speed Grade: -12
Minimum period: 2.956ns (Maximum Frequency:338.289MHz)
Minimum input arrival time before clock: 2.327ns
Maximum output required time after clock: 3.874ns
Maximum combinational path delay: No path found
上述四条信息即为静态时序分析中的4个要点，分别为：
最小周期，即最大工作频率；
最小输入数据建立时间，可理解为数据信号的建立时间（从FPGA外部看进来），该时间只针对模块的输入数据信号有效，即表示模块外部输入的数据在时钟信号有效沿到来前应该保持稳定不变的最小时间。
最大输出数据时间，表示从对数据赋值的clk有效沿开始，模块输出管脚达到稳定的最大时间，该时间只对模块的输出信号有效。
最大组合逻辑延迟时间，该时间可作为关键路径延迟时间，若不存在关键路径，则不显示。
针对上述4点可大概估计设计的最大工作频率，以及影响最大工作频率提高的关键路径，进一步根据以下信息确定关键路径，从而对关键路径进行优化，以提高最大工作频率。而最小输入数据建立时间可作为对模块输入数据的时序要求，为了提高模块性能，往往希望该时间越短越好，可进一步根据以下信息确定影响该时间的路径，加以优化。
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.956ns (frequency: 338.289MHz)
Total number of paths / destination ports: 11500 / 4354
这部分提到的信号及其具体延迟信息，就是影响模块最大工作频率的关键信号和路径，若想进一步提高模块工作频率，可针对该信号或路径进行优化。
-------------------------------------------------------------------------
Delay: 2.956ns (Levels of Logic = 5)
Source: coef/BU13 (RAM)
Destination: fir/blk00000003/blk000007c7 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: coef/BU13 to fir/blk00000003/blk000007c7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (NetName)
---------------------------------------- ------------
RAMB16:CLKA->DOPA0 1 1.647 0.554 BU13 (N364)
LUT4:I0->O 1 0.147 0.000 BU246 (N8760)
MUXF5:I0->O 1 0.291 0.000 BU252 (N8655)
MUXF6:I1->O 1 0.300 0.000 BU254 (dout<8>)
end scope: 'coef'
begin scope: 'fir'
begin scope: 'blk00000003'
FDRE:D 0.017 blk000007c7
----------------------------------------
Total 2.956ns (2.402ns logic, 0.554ns route)
(81.3% logic, 18.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 74 / 74
这一部分提到的信号及其延迟信息，就是影响最小输入数据建立时间的关键信号或者路径，若要减小该时间，可针对这些信号或路径进行优化。
-------------------------------------------------------------------------
Offset: 2.327ns (Levels of Logic = 2)
Source: reset (PAD)
Destination: coef_ram_addr_init_0 (FF)
Destination Clock: clk rising
Data Path: reset to coef_ram_addr_init_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (NetName)
---------------------------------------- ------------
IBUF:I->O 16 0.754 0.609 reset_IBUF(reset_IBUF)
LUT2:I0->O 14 0.147 0.409 coef_ram_addr_init_and00001 (coef_ram_addr_init_and0000)
FDE:CE 0.409 coef_ram_addr_init_0
----------------------------------------
Total 2.327ns (1.310ns logic, 1.017ns route)
(56.3% logic, 43.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 42 / 42
同理，这一部分提到的信号及其延迟信息是影响模块数据最大输出时间的关键。
-------------------------------------------------------------------------
Offset: 3.874ns (Levels of Logic = 2)
Source: fir/blk00000003/blk0000089b (FF)
Destination: rfd (PAD)
Source Clock: clk rising
Data Path: fir/blk00000003/blk0000089b to rfd
Gate Net
Cell:in->out fanout Delay Delay Logical Name (NetName)
---------------------------------------- ------------
FDSE:C->Q 9 0.272 0.347 blk0000089b (rfd)
end scope: 'blk00000003'
end scope: 'fir'
OBUF:I->O 3.255 rfd_OBUF (rfd)
----------------------------------------
Total 3.874ns (3.527ns logic, 0.347ns route)
(91.0% logic, 9.0% route)
=========================================================================
上述时钟分析只是综合后的时序，与最终硬件上跑的时序是有差别的。关于最小数据输入时间和最大数据输出时间的定义以及其他相关内容可参考以下博客内容：http://blog.ednchina.com/cqcrr/143490/message.aspx