The Cadence GDDR6 PHY includes two separate and independent register interfaces. Only one of them is expected to be used for a given application; The other should be tied off, inputs should be held in-active, and outputs should not be connected to anything (leave floating). The connected interface is used to read and write both initialization and status parameters to the PHY. These parameters hold timing values to correctly capture and send data from and to the DRAM devices as well as programmable settings for other features configured for the PHY.
The PHY TOP apb_intfc_en pin is used to select which interface to use. When this pin is tied to 0, the Denali interface is used. When tied to 1, the APB interface is used.
Denali PHY Register Interface
The Cadence GDDR PHY Denali register interface consists of a synchronous address-mapped read/write port.
Denali Operation
A write to these registers is only accepted when the phy_reg_command_ready signal is high, indicating that the PHY is able to accept the new command. The write consists of a register address (phy_reg_addr), a byte mask (phy_reg_mask), the intended data (phy_regin), an assertion of the phy_reg_write signal and a phy_reg_command_valid indicator. The register write is accepted as long as both phy_reg_command_ready and phy_reg_command_valid are asserted; there is no response from the PHY indicating that the command was accepted. The phy_reg_command_ready and phy_reg_command_valid are not necessarily active in the same cycle, when the register master recognizes a phy_reg_command_ready it can generate a valid register request to the PHY. Pipeline stages between the register master and the PHY's register bus can create latency between the ready and valid signals.
Due to the transition of the register bus from the controller clock domain to the PHY clock domain, the phy_reg_command_ready signal is asserted for 1 cycle every 8 cycles.
A read is also accepted only when phy_reg_command_ready has been asserted prior to phy_reg_command_valid. A read consists of an address (phy_reg_addr) and the de-assertion of the phy_reg_write signal when the phy_reg_command_valid signal is asserted. As with the write command, the read command is accepted as long as phy_reg_command_ready has been asserted and phy_reg_command_valid is asserted. After the phy_reg_command_valid for the read command has been sent, an additional phy_reg_command_ready signal may appear on the register bus before remaining de-asserted until the completion of the read operation. This does not mean that an additional register command can be sent; once a read command has been sent to the PHY, no other commands should be sent until the phy_regout_valid signal has been de-asserted. When the PHY is ready to return the data for the read, it asserts the phy_regout_valid signal along with the data on the phy_regout bus. The user interface must assert the phy_regout_accept signal when the data has been received. Read data is returned in the order that the commands are received.
All register interface signals are captured on the rising edge of the clock.
After a register request enters the PHY, it is decoded and routed to the appropriate slice or the top level parameter module. The request is then serviced within the slice or top level parameter module.
APB Register Interface
The Cadence GDDR PHY APB register interface consists of an industry standard ABP write/read interface. The maximum phy_reg_PCLK frequency is 400 Mhz. 4.6 PHY Scan Test Pins APB Register Interface Signals
