GDDR6 PHY is implemented with a slice-based architecture. Individual slice components are hardened and placed multiple times at the PHY level. A subset of the overall PHY logic is synthesized and placed outside of the slice components.
GDDR6 PHY is delivered as a hard PHY. It consists of:
• A memory controller interface
• An external register interface (configuration and test)
• PHY control block (initialization and calibration logic)
• Two 16-bit data channel slices
• Two 11-bit command/address (CA) channel slices
• A clock slice
The data channel slice converts data read and write signals to and from the controller interface (DFI) into data read and write signals required by the memory interface. The CA channel slice converts command and address signals in a way similar to the data channel slice
The top-level blocks contain Memory Controller (MC) interface logic and general PHY control, which then communicates to the slices.
• DFI（DDR Phy Interface） Interface to the MC
• JTAG Interface to the SoC
• Register Interface to the MC
• PHY Independent Training (PI)
• Common Slice, including Clock Control, I/O Pad Calibration, and PLL
• PHY Control
• PHY Registers
The slice-based architecture consists of three slice types, which interface to the DRAM GDDR6 device channels A and B. Each slice has digital logic and analog logic.
• Data Channel Slice: 16 bits wide containing two 8-bit bytes, each GDDR6 channel has its own slice.
• CA Channel Slice: 13 bits wide, each GDDR6 channel has its own slice.
• CLK Slice: Shared between both GDDR6 channels.
DFI Interface
The DFI Interface uses DFI 5.0 protocol to interface the MC to the PHY. The frequency ratio for the DFI commands is 1:2. The frequency ratio for the DFI DATA is 1:8. There is a 1-stage pipeline to help timing closure in the DFI interface in both directions.
JTAG Interface
The JTAG Interface can be used to write and read all PHY internal registers, execute BIST loopback of all GDDR6 Device pins, and initialize all PHY internal logic, including all the slice analog logic. However, It cannot be used to generate any GDDR6 write or read traffic.
Register Interface
The Register Interface is used to write and read any PHY internal register. There is a 1-stage pipeline to help timing closure in both directions.
PHY Independent
The PHY Independent Training block is used to perform all GDDR6 training without any assistance from the MC. It is capable of generating appropriate Mode Writes to the Device, and handle refresh requirements during training as needed. However, the MC is expected to issue appropriate Refresh commands to maintain memory device refresh requirements and the PI will forward these commands to the memory device.
Common Module
• The Clock Control block manages the switching of clocks between the external supplied reference clock, or the internally generated PLL clock. Clock switching is always glitchless, using appropriate clock gates. The PLL is programmed to generate internally derived 1X/2, 1X, 2X, and 8X clocks, with the 1X clock being used externally by the MC. The 8X clocks are used by the slice logic.
• The I/O Pad Calibration block is used to generate PVT calibration codes used by all I/O Pads. It is executed once at a minimum during power on reset, and may be ongoing in either a manual or automatic interval mode.
• The PLL block contains the only PLL in the PHY, which produces all internal clocks, the external GDDR6 device clock, and the external MC clock. It uses an external 100 Mhz reference clock, which is also used internally by all PHY logic during times of PLL programming and frequency switching.
PHY Control
The PHY Control block contains general PHY top miscellaneous logic.
PHY Registers
The PHY Registers block contains address decoding to distribute incoming register access to the appropriate internal PHY block:
• PHY Independent
• Data Slice
• CA slice
• CLK slice
• I/O Pad calibration
• PLL control.
The source of register access can be either from the MC or the JTAG interface.
Data Channel Slice
The Data Channel slice contains the GDDR6 device I/O pads and data path for the DQ, DBI, EDC and WCK signals. Each slice contains 2 bytes, for a total of 16 bits. Each slice connects to one channel (A or B) of the GDDR6 device.
Command/Address (CA) Channel Slice
The CA Channel Slice contains the GDDR6 device I/O pads and data path for the CA, CABI_n, and CKE_n signals. Each slice connects to one channel (A or B) of the GDDR6 device. 2.4.10 CLK Slice The CLK slice contains the GDDR6 device I/O pads and data path for the CK and RESET_n signals. This single slice is shared by both channels A and B of the GDDR6 device.
