The Cadence Cadence® Denali® GDDR6 PHY is implemented with a slice-based architecture.
Individual slice components are hardened and placed multiple times at the PHY level.
A subset of the overall PHY logic is synthesized and placed outside of the slice components.
Functional Blocks
The slice-based architecture consists of the following components:
• Data channel slice (2 bytes, 16 DQ, 2 DBI, 2 EDC, 2 WCK)
• CA channel slice 11 CA, CABI_n, CKE_n
• Clock slice (1 CK, 1 RESET_N)
The non-slice based architecture consists of the following components:
• Common Module (I/O Pad Cal, PLL, ATB)
• PHY Independent
• Clock generation and control
• DFI Delay • Register Delay
• Parameter interface
The single PLL supplies both PHY and MC clocks.
Data Channel Slice
The data channel slice transfers data between the memory controller and the GDDR6 SDRAM devices. The data channel slice is a 16-bit wide design that interfaces to the DQ, DBI_n, WCK, and EDC connections of the DRAM and is duplicated to connect to a GDDR6 memory device.
The data channel slice supports 2 bytes of data where the interface for each byte is 8 DQ/1 DBI_n/1 WCK/1 EDC. The write data path logic (from DFI to pads) and the read data path logic (from pads to DFI) are contained within the data channel slice. Termination and directional controls for the data path related I/Os are also contained in the slice.
Other features supported within the data channel slice include: •
ILL per bit slice
• PI per TX/RX per DQ/DBI_n/EDC/WCK
• Per bit delay line control on the read and write paths
• DFI frequency conversion between controller clock and memory clock
• Training:
• Write DQ data eye training
• Read training (data eye training)
• WCK to CK training
Command/Address (CA) Channel Slice
The CA channel slice transfers the command/address information between the memory controller and the GDDR6 SDRAM devices.
The slice contains 11 CA bits, 1 CABI_n bit and 1 CKE_n bit.
The command/address write data path logic (from DFI to pads) and the read data path logic (loopback only) are contained within the CA channel slice.
Termination and directional controls for the address path related I/Os also reside in the slice.
Other features supported within the CA channel slice include:
• ILL/PI per TX/RX per CA/CABI_n/CKE_n
• Per bit delay line control on the read and write paths
• DFI frequency conversion between controller clock and memory clock
• Training
• CA training