module的嵌套調用與執行順序分析(systemverilog)

在systemverilog中，module可以被嵌套調用。最頂層的module名應與vsim.do中指定的模塊名相同：vsim -t fs -novopt sim_top glbl，此表示仿真頂層模塊名爲：sim_top.仿真是從頂層模塊中執行，其中的always,initial，模塊實例化等有實際意義的語句均會被執行，但function、task等語句只有在調用時纔會被執行，就跟c語言中相同。

tips:在questa10.2中，當變量在聲明時缺省是automatic，但賦有初值的變量在定義時需指定automatic or static.

Examp:

`timescale 1ns/1ps

module module1();
task frame();
automatic byte preamble[1:7]='{10,10,10,10,10,10,10};
$display("4th byte of preamble=%0b\n",preamble[4]);
endtask
initial
begin
frame();
$display("%m : Inside Module1 ");
//$root.top.U.U.frame();//using frame within instance U within instance U
end
endmodule

module module2();
task vlanframe();
typedef struct {bit [15:0]tag_type;bit [15:0]control_info;}vlan_byte;
automatic vlan_byte v1='{'d33024,11110000};
automatic vlan_byte v2 [0:1]='{'{'d33024,00011100},'{'h8100,00111111}};
$display("tag_type=%0h control_info=%0h",v1.tag_type,v1.control_info);
$display("tag_type=%0h control_info=%0h",v2[0].tag_type,v2[1].control_info);
$display("%m : Inside Module2");
endtask
module1 U1 ();
initial
begin
vlanframe();//using frame within top instance U2
U1.frame();//using frame within top instance U
end
endmodule

module sim_top();
task print();								
$display("%m : Inside Top Module ");
endtask

module2 U(); //instantiates the local module2 declared above
module1 U2(); //instantiates the local module1 declared above
endmodule

output:

# 4th byte of preamble=1010
# 
# sim_top.U.U1 : Inside Module1 
# tag_type=8100 control_info=8670
# tag_type=8100 control_info=b207
# sim_top.U.vlanframe : Inside Module2
# 4th byte of preamble=1010
# 				
# 4th byte of preamble=1010
# 
# sim_top.U2 : Inside Module1