systemverilog 中多種always

在systemverilog中，仍然支持verilog中的always,但同時新增了always_comb and always_latch blocks，在time 0時刻always會被執行一次，並且always中被賦值的變量不能再在其他process中被賦值。

SystemVerilog provides a special always_comb procedure for modeling combinational logic behavior，always_comb特定用於combinational logic behavior. For example:

`timescale 1 ns / 1 ps 

module sim_top();
reg data_prsnt,data_prev;
reg bip;
initial begin
   data_prsnt = 0;
#1 data_prsnt = 1;
#1 data_prev = 1;
#5 data_prsnt = 0;
#5 data_prsnt = 0;
#1 $finish;
end
always_comb
begin : PARITY
bip = data_prsnt ^data_prev;
$display("@%g data_pr= %b data_previous = %b bit_interleaved_parity = %b", $time, data_prsnt, data_prev, bip);
end
endmodule

output：

# @0 data_pr= 0 data_previous = x bit_interleaved_parity = x
# @1 data_pr= 1 data_previous = x bit_interleaved_parity = x
# @2 data_pr= 1 data_previous = 1 bit_interleaved_parity = 0
# @7 data_pr= 0 data_previous = 1 bit_interleaved_parity = 1

從例中可知，在time 0時刻always_comb會被執行一次，然後當always_comb內的變量值發生改變(與之前值不同，若被賦值之前相同值不會觸發)時會被再次觸發。在always_comb與always_latch中不能進行timing control,即下面進行delay #5不對，但在always中可以。

always_comb
#5 bip = data_prsnt ^data_prev;