VCS RTL Verification
VCS 數字邏輯仿真器和VCS MX混合HDL語言仿真器都是Synopsys的智能RTL驗證解決方案的基石。VCS是業界領先的仿真器,支持本徵斷言(native assertion)描述、自動測試平臺生成技術(testbench)、以及代碼和斷言覆蓋引擎,確保智能化驗證的實現。VCS中本徵代碼支持 (Native)技術確保了設計驗證的效率、性能和質量,並縮短了驗證週期。VCS中的本徵代碼技術實現了在單一工具中,支持可驗證性設計(DFV),及
覆蓋率驅動和約束的隨機激勵生成。其本徵對斷言的支持和所包含的豐富的斷言檢查工具庫保證了設計人員能夠方便地採用DFV技術來查找錯誤和提高驗證質量。 此外,斷言可以作爲設計要求重複利用,在Synopsys的混合RTL規則驗證產品Magellan中進行形式驗證。
VCS對專用集成電路(ASIC)生產商的建模和仿真籤核(Sign-off)提供了支持。
VCS對統一的設計和驗證語言標準SystemVerilog提供支持。SystemVerilog增強了設計人員的能力,加快了驗證速度並提高了驗證的質量。
對於要求在RTL環境中使用SystemC模型進行驗證的設計團隊,VCS提供了支持OSCI SystemC的直接內核接口(DKI)和支持System Studio的直接內核接口(DKI)。
主要優點:
- 本徵測試平臺(testbench)、斷言和完備的覆蓋率測試技術,爲Verilog 和混合HDL驗證帶來2-5倍的性能提升
- 爲SystemVerilog設計和基於斷言的驗證提供支持,確保更高的設計和驗證效率
- 提供最高的性能和容量,加快產品上市週期
- 通過集成NanoSim實現了具有最高處理能力的混合信號仿真環境
- 採用單個統一工具,實現Verilog和混合HDL RTL及SystemC的支持
- 支持所有主要的UNIX和Linux平臺
VCS快速參考
1. Unix環境設置:
if (-e ${VCS_HOME}/bin/environ.csh) then
source ${VCS_HOME}/bin/environ.csh
endif
export VCS_HOME
. ${VCS_HOME}/bin/environ.sh
2. 執行仿真:
verilog_source_fileis the name of the Verilog source file to be analyzed+define+macrodefines any macros needed for ‘ifdef conditions defined in theVerilog source.-f filenameReads a file, filename, and passes all arguments from that file onto the vlogan command line.-l logfileRedirects all output from vlogan into the specified logfile.-qDisables verbose messaging.-v library_fileSearches for unresolved module references in file library_file-y search_dirSearches for unresolved module references in the directorysearch_dir+libext+extUses the extension ext when searching library directories-work logical_librarySpecifies the VHDL logical library to place the Verilog modulesinto. Any VHDL source that instances this Verilog code canreference this VHDL library to find the module.-resolveBy default, vlogan does not resolve instantiated VHDL designunits. This option tells vlogan to resolve VHDL design units aswell. If this option is not used, any VHDL design units areresolved during compilation.-sverilogEnables the analysis of SystemVerilog source code+vhdllib+libsSearch libraries for VHDL components in case they wereanalyzed in library other than “WORK”.(use with -resolve)+reflib+libsSearch libraries for Verilog components in case they wereanalyzed in library other than “WORK”. (use with -resolve).+librescanSearch from beginning of library list for all undefined Verilogmodules.+notimingchecksSpecifies no timing simulation (used for parsing only)+nospecifySpecifies no path delays (used for parsing only)
+v2kEnables the use of new Verilog constricts in the 1364-2001standard.-full64Compiles the design in 64 bit mode and creates a 64 bitexecutable for simulating in 64 bit mode.-cm_libs yv|celldefineSpecifies compiling for coverage source files in Verilog librarieswhen you include the yv argument. Specifies compiling forcoverage module definitions that are under the ‘celldefinecompiler directive when you include the celldefine argument.You can specify both arguments using the plus (+) delimiter.+cli+[module_name=]1|2|3|4Enable CLI debugging.1 enables you to see the values of nets and registers and depositvalues to registers.2 also enables breakpoints on value changes of nets and registers.3 also enables you to force a value on nets.4 also enables you to force a value on a register.You can specify a module to enable CLI debugging only forinstances of the module.-lineEnables stepping through the code and source line breakpoints inDVE.+vpiEnables the use of VPI PLI access routines.-sverilogEnables the analysis of SystemVerilog source code-ntb_opts keyword_argumentThe keyword arguments are as follows:checkReports error, during compilation or simulation, when there isan out-of-bound or illegal array access.dep_checkEnables dependency analysis and incremental compilation.Detects files with circular dependencies and issues an errormessage when VCS cannot determine which file to compilefirst.no_file_by_file_ppBy default, VCS does file by file preprocessing on each inputfile, feeding the concatenated result to the parser. Thisargument disables this behavior.print_deps[=filename]Enter this argument with the dep_check argument. Thisargument tells VCS to display the dependencies for the sourcefiles on the screen or in the file that you specify.tb_timescale=valueSpecifies an overriding timescale for the testbench. Thetimescale is in the Verilog format (for example,10ns/10ns).use_sigpropEnables the signal property access functions. (for example,vera_get_ifc_name()).vera_portnameSpecifies the following:The Vera shell module name is named vera_shell.The interface ports are named ifc_signal.Bind signals are named, for example, as: \if_signal[3:0].You can enter more than one keyword argument, using the +delimiter, for example:-ntb_opts use_sigprop+vera_portname+nospecifySpecifies no path delays (used for parsing only)-override_timescale=time_unit/time_precisionOverrides the time unit and a precision unit for all the‘timescale compiler directives in the source code and,like the -timescale option, provides a timescale for allmodule definitions that precede the first ‘timescalecompiler directive. Do not include spaces when specifyingthe arguments to this option.-assert keyword_argumentThe keyword arguments are as follows:dumpoffDisables the dumping of SVA information in the VPD fileduring simulation.filterBlocks reporting of trivial implication successes. Thesehappen when an implication construct registers a success onlybecause the precondition (antecedent) portion is false (and sothe consequence portion is not checked). With this option,reporting only shows successes in which the whole expressionmatched.finish_maxfail=NTerminates the simulation if the number of failures for anyassertion reaches N. N must be supplied, otherwise no limit isset.global_finish_maxfail=NStops the simulation when the total number of failures, fromall SystemVerilog assertions, reaches N.maxcover=NDisables the collection of coverage information for coverstatements after the cover statements are covered N number oftimes. Nmust be a positive integer, it can’t be 0.+incdir+directory+Specifies the directories that contain the files you specified withthe ‘include compiler directive. You can specify more that onedirectory, separating each path name with the “+” character.-y directory_pathnameSpecifies a Verilog library directory to search for moduledefinitions.+define+macro_name=value+Defines a text macro. Test for this definition in your Verilogsource code using the ‘ifdef compiler directive.-cm line|cond|fsm|tgl|pathSpecifies compiling for the specified type or types of coverage.The arguments specifies the types of coverage:lineCompile for line or statement coverage.condCompile for condition coverage.fsmCompile for FSM coverage.tglCompile for toggle coverage.pathCompile for path coverage.-cm_noconstTells VCS not to monitor for conditions that can never be met orlines that can never execute because a signal is permanently at a 10r 0 value.-cm_cond argumentsModifies condition coverage as specified by the argument orarguments:basicOnly logical conditions and no multiple conditions.stdThe default: only logical, multiple, sensitized conditions.fullLogical and non-logical, multiple conditions, no sensitizedconditions.allopsLogical and non-logical conditions.eventSignals in event controls in the sensitivity list position areconditions.anywidthEnables conditions that need more than 32 bits.sopSpecifies condition SOP coverage. It also tells VCS that whenit reads conditional expressions that contain the ^ bitwiseXOR and ~^ bitwise XNOR operators, it reduces theexpression to negation and logical AND or OR.forEnables conditions in for loops.tfEnables conditions in user defined tasks and functions.You can specify more than one argument. If you do use the + plusdelimiter between arguments, for example:-cm_cond basic+allops-cm_tgl mdaEnables toggle coverage for Verilog 2001 multidimensionalarrays and SystemVerilog unpacked arrays. Not requires forpacked SystemVerilog arrays.-P pli.tabSpecifies a PLI table file.+libext+extensionSpecifies that VCS only search the source files in a Veriloglibrary directory with the specified extension. You can specifymore than one extension, separating each extension with the “+”character. For example, +libext++.v specifies searches libraryfiles with no extension and library files with the .v extension.Enter this option when you enter the -y option.-v filenameSpecifies a Verilog library file to search for module definitions.
-cm line|cond|fsm|tgl|path|assertSpecifies monitoring for the specified type or types of coverage.The arguments specifies the types of coverage:lineMonitor for line or statement coverage.condMonitor for condition coverage.fsmMonitor for FSM coverage.tglMonitor for toggle coverage.pathMonitor for path coverage.branchMonitor for branch coverage.assertMonitor for SystemVerilog assertion coverage.If you want VCS to monitor for more than one type of coverage,use the plus (+) character as a delimiter between arguments, forexample:-cm line+cond+fsm+tgl-cm_name filenameSpecifies the name of the report files.
-notimingchecks +nospecify -override_timescale=1ns/10ps \
-assert vpiSeqFail -assert enable_diag +define+ASSERT_ON \
+incdir+/home/tools_new/synopsys/VCS-D-2010.06_AMD64/packages/sva+
-y /home/tools_new/synopsys/VCS-D-2010.06_AMD64/packages/sva \
+define+DEBUG_OPTION +define+MAX_ERR_NUM=10000 -cm_noconst -cm_cond full -cm_tgl portsonly \
-P /home/tools_new/novas/Novas2010_verdi/share/PLI/vcs2006.06/LINUX64/debussy.tab \
/home/tools_new/novas/Novas2010_verdi/share/PLI/vcs2006.06/LINUX64/pli.a \
+libext+.v+
+incdir+~/project/Berry/vmodel/common/rtl+~/project/Berry/vmodel/common/tb+~/project/Berry/vmodel/vdu/tb~/project/Berry_gen/vmodel/vdu/tb+ \
-y ~/project/Berry/vmodel/common/rtl
-y ~/project/Berry/vmodel/common/tb
-y ~/project/Berry/vmodel/vdu/rtl
-y ~/project/Berry/vmodel/vdu/tb
-y ~/project/Berry_gen/vmodel/vdu/tb
-y ~/project/Berry/vmodel/mbist/rtl \
-y /home/tools_old/Misc/Xilinx/ISE_DS/ISE/verilog/src/unisims \
-v /home/TSMC/TSMC-CL013G/SC_metro_fb_060907/aci/sc-m/verilog/tsmc13_m.v \
/home/tools_old/Misc/Xilinx/ISE_DS/ISE/verilog/src/glbl.v
~/project/Berry/vmodel/vdu/tc/vdu_unit_960h_03.v
-file ~/project/Berry/vmodel/vdu/scripts/vcs_option
## file: vcs_option
3. PLI Table的格式:
格式如下:call=functioncheck=functionmisc=functiondata=integersize=numberargs=nocelldefineplipersistent
acc=(+=)|-=|:=capibities:module_name[+]|%CELL|%TASK|*其中:acc 關鍵字=(+=)|-=|:= add/remove/changecapibilities 冒號分隔PLI函數可用的ACC功能:r/readrw/read_writecbk/call_back...# VCS配置文件可用來指定對設計的每個部分採用Radiant technology optimization 和 two state simulation.文件語法如下:module{list_of_module_identifiers} {list_of_attributes};instance{list_of_module_identifiers} {list_of_attributes};tree [(depth)]{list_of_module_identifiers} {list_of_attributes};Radiant technology的屬性:noOptnoPortOptOptPortOpttwo state simulation的屬性:2value4value