控制SystemVerilog Assertion的關閉打開

module my_control ();
  initial begin : disable_assertions_during_reset
    $display ("%0t %m Disabling assertions during init..", $time);
    $assertoff (0, top_tb.cpu_rtl_1);
    @ (top_tb.reset_n === 1'b1);
    $display ("%0t %m Enabling assertions after init..", $time);
    $asserton (0, top_tb.cpu_rtl_1);
   end
endmodule : my_control
module top_tb;
  logic clk =1’b0, reset_n = 1’b0;
  bus_if b_if; 
  cpu_rtl cpu_rtl_1(clk, reset_n, .*); // Instantiation of cpu module
  my_control my_control_1(); // instantiation of assertion control
..
endmodule : top_tb

在reset期間關閉assertion，reset後打開assertion。使用系統函數$asserton，$assertoff即可。