使用VIM，你可以完全解放鼠标，只用到大键盘就可以完成所有操作，非常的方便快捷，可以让我更加专注设计。
GVIM的配置，只需要配置_vimrc文件即可，想要什么功能都可以自己配置，比如我喜欢的光标不闪烁；括号自动补全，并跳出括号；列操作；在insert模式下，使用pp自动补全，hh左移，jj下移等。
以下内容分两部分，一是GVIM自带的命令汇总，二是自定义的规则，便于我快捷写verilog代码，可以快速添加文件注释，module模块，宏定义和接口信号声明，代码主体部分，组合逻辑，异步/同步时序逻辑设计等
注：<C-r>是Ctrl+r的组合键
// *********************************************************************
// File Name : GVIM.txt
// Author : YYB
// Create Date : 2019-12-05 15:41
// Last Modified : 2019-12-05 15:41
// Description : GVIM自定义规则汇总
// Notes :
// *********************************************************************
GVIM命令：
normal模式和insert模式:
normal模式下的命令:
i --> 进入insert模式，按ESC回到normal模式
x --> 删除当前光标所在的一个字符
:wq --> 存盘+退出(:w 存盘，:q 退出)(:w后可以跟文件名)
dd --> 删除当前行，并把删除的行存在剪贴板里
p --> 粘贴剪贴板
hjkl --> 左下上右
:help <command> --> 显示相关命令的帮助
各种插入模式:
a --> 在光标后插入
O --> 在当前行前插入一个新行
o --> 在当前行后插入一个新行
简单的移动光标：
0 --> 数字零，到行头
^ --> 到本行第一个不是blank字符的位置(所谓blank字符就是空格、tab、换行、回车等)
$ --> 到本行行尾
g_ -->到本行最后一个不是blank字符的位置
/pattern --> 搜索pattern的字符串（如果搜索出多个匹配，可按n键到下一个）
:noh --> 取消搜索字符串的高亮显示
拷贝/粘贴:
yy --> 拷贝当前行于剪贴板
p --> 粘贴，当前位置之后
Undo/Redo:
u --> undo
<C-r> --> redo
打开/保存/退出/改变文件:
:e <path/to/file> --> 打开一个文件
:wq --> 存盘+退出(:w 存盘，:q 退出)(:w后可以跟文件名)
:q! --> 退出不保存
:saveas <path/to/file> --> 另存为<path/to/file>
重复自己:
. --> (小数点)可以重复上一次的命令
N<command> --> 重复某个命令N次
比如：2dd --> 删除2行 3p --> 粘贴文本3次
光标移动更有效率:
gg --> 到第一行
NG --> 到第N行
G --> 到最后一行
按单词移动光标:
w --> 到下一个单词的开头
e --> 到下一个单词的结尾
最强的光标移动:
% --> 匹配括号移动，包括(),{},[]
*和# --> 匹配光标所在单词，移动光标到下一个(上一个)匹配单词
禁止光标不闪烁的方法: set gcr=i:ver15-blinkon0 (insert模式下)
set gcr=n:block-blinkon0 (normal模式下)
块操作:
典型的操作:0 <C-q> <hjkl> I--[ESC] (块操作在句首处输入--)
自动补齐:
在insert模式下，输入一个词的开头，然后按<C-p>或<C-n>，自动补齐就出现了。
分屏:
输入:split (创建横分屏)(可以使用:sp代替)
输入:vsplit (创建垂直分屏)(可以使用:vs代替)
可以使用hjkl切换分屏;
关闭其他分屏，保留当前分屏：ctrl+w和o
改变分屏尺寸：ctrl+w和+ (增大尺寸)
ctrl+w和- (减小尺寸)
自定义的规则:
在括号中移动的快捷方式:现在括号可以自动补全了，按ESC可以跳出括号
关键字匹配代码块
在insert模式下，
pp --> 自动补全
hh --> 左移
jj --> 下移
kk --> 上移
ll --> 右移
ii --> <ESC>
在normal模式下，qq --> <C-q>(列操作),所以列操作就变为:
进入normal模式，qq <hjkl> I <内容> <ESC>
以下是编写verilog的快捷方式:
F2 --> 文件头注释
Module --> module模块
Define --> 宏定义和接口信号声明
Code --> 代码主体部分
zuhe --> 组合逻辑
yibu --> 异步时序逻辑
tongbu --> 同步时序逻辑
input对齐规则:
input48 --> input [47:0]
input32 --> input [31:0]
input31 --> input [30:0]
...
input2 --> input [1 :0]
input --> input
output对齐规则类似于input
举例:output32 --> output wire [31:0]
outputreg32 --> output reg [31:0]
wire对齐规则类似于input
reg对齐规则类似于input
_vimrc文件如下：
" ***********************************************************************
" * Author : YYB
" * Create time : 2019-12-4 22:37
" * Last modified : 2018-12-4 22:37
" * Filename : _vimrc
" * Description : 配置GVIM，为快速编写verilog代码
" * *********************************************************************
set nocompatible
source $VIMRUNTIME/vimrc_example.vim
source $VIMRUNTIME/mswin.vim
source $VIMRUNTIME/colors/desert.vim
behave mswin
"设置光标不闪烁
set gcr=i:ver15-blinkon0
set gcr=n:block-blinkon0
"let g:indent_guides_enable_on_vim_startup = 1
"--------------------------------------------------------------------------------
"------------------------------对齐规则------------------------------------------
"--------------------------------------------------------------------------------
set nu!
set sw=4
set ts=4
set et
set nobackup
"注释换行不自动添加注释
au FileType c,cpp,verilog setlocal comments-=:// comments+=f://
set paste
"自动补全括号，按TAB跳出括号
inoremap ' ''<ESC>i
inoremap " ""<ESC>i
inoremap ( ()<ESC>i
inoremap [ []<ESC>i
inoremap < <><ESC>i
inoremap { {<CR>}<ESC>O
"设置跳出自动补全的括号
func SkipPair()
if getline('.')[col('.') - 1] == ')' || getline('.')[col('.') - 1] == ']' || getline('.')[col('.') - 1] == '"' || getline('.')[col('.') - 1] == "'" || getline('.')[col('.') - 1] == '}' || getline('.')[col('.') - 1] == ">"
return "\<ESC>la"
else
return "\t"
endif
endfunc
" 将TAB键绑定为跳出括号
inoremap <TAB> <c-r>=SkipPair()<CR>
:imap pp <C-p>
:imap hh <Left>
:imap jj <Down>
:imap kk <Up>
:imap ll <Right>
:imap ii <Esc>
:map qq <C-q>
"--------------------------------------module----------------------------------
"------------------------------------------------------------------------------
"--------------------------------------module----------------------------------
:ab Define //======================================================================<Enter>//************** Define Parameter and Internal Signals *****************<Enter>//======================================================================<Enter><ESC>i
:ab Code //======================================================================<Enter>//**************************** Main Code *******************************<Enter>//======================================================================<Enter><ESC>i
:ab Module module (<Enter><Enter>);<Enter><Enter><Enter><Enter><Enter><Enter>endmodule<Esc>
":ab Zh ii0d$ialways @(*) begin <ESC>dwa<Enter> end<Esc>0dwk$a
"--------------------------------------时序逻辑----------------------------------------"
"组合逻辑，使用快捷方式zuhe
:ab zuhe always @(*)begin<Enter>if ()begin<Enter><Enter>end<Enter>else begin<Enter><Enter>end<Enter>end
"异步时序逻辑，使用快捷方式yibu
:ab yibu always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter><Enter>end<Enter>else if()begin<Enter><Enter>end<Enter>else begin<Enter><Enter>end<Enter>end
"同步时序逻辑，使用会计方式tongbu
:ab tongbu always @(posedge clk)begin<Enter>if(!rst_n)begin<Enter><Enter>end<Enter>else if()begin<Enter><Enter>end<Enter>else begin<Enter><Enter>end<Enter>end
"---------------------------------------计数器-----------------------------------------"
:ab Jsq iid0d$i//cnt<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt <= 0;<Enter>end<Enter>else if(add_cnt)begin<Enter>if(end_cnt)<Enter>cnt <= 0;<Enter>else<Enter>cnt <= cnt + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt<Tab><Tab>=<Tab><Tab>; <Enter>assign end_cnt<Tab><Tab>=<Tab><Tab>add_cnt && cnt == ;
:ab Jsq2 iid0d$i//cnt0<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt0 <= 0;<Enter>end<Enter>else if(add_cnt0)begin<Enter>if(end_cnt0)<Enter>cnt0 <= 0;<Enter>else<Enter>cnt0 <= cnt0 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt0<Tab><Tab>=<Tab><Tab>;<Enter>assign end_cnt0<Tab><Tab>=<Tab><Tab>add_cnt0 && cnt0 == ;<Enter><Enter>//cnt1<Enter>always @(posedge clk or negedge rst_n)begin <Enter>if(!rst_n)begin<Enter>cnt1 <= 0;<Enter>end<Enter>else if(add_cnt1)begin<Enter>if(end_cnt1)<Enter>cnt1 <= 0;<Enter>else<Enter>cnt1 <= cnt1 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt1<Tab><Tab>=<Tab><Tab>end_cnt0;<Enter>assign end_cnt1<Tab><Tab>=<Tab><Tab>add_cnt1 && cnt1 == ;
:ab Jsq3 iid0d$i//cnt0<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt0 <= 0;<Enter>end<Enter>else if(add_cnt0)begin<Enter>if(end_cnt0)<Enter>cnt0 <= 0;<Enter>else<Enter>cnt0 <= cnt0 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt0<Tab><Tab>=<Tab><Tab>;<Enter>assign end_cnt0<Tab><Tab>=<Tab><Tab>add_cnt0 && cnt0 == ;<Enter><Enter>//cnt1<Enter>always @(posedge clk or negedge rst_n)begin <Enter>if(!rst_n)begin<Enter>cnt1 <= 0;<Enter>end<Enter>else if(add_cnt1)begin<Enter>if(end_cnt1)<Enter>cnt1 <= 0;<Enter>else<Enter>cnt1 <= cnt1 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt1<Tab><Tab>=<Tab><Tab>end_cnt0;<Enter>assign end_cnt1<Tab><Tab>=<Tab><Tab>add_cnt1 && cnt1 == ;<Enter><Enter>//cnt2<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt2 <= 0;<Enter>end<Enter>else if(add_cnt2)begin<Enter>if(end_cnt2)<Enter>cnt2 <= 0;<Enter>else<Enter>cnt2 <= cnt2 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt2<Tab><Tab>=<Tab><Tab>end_cnt1;<Enter>assign end_cnt2<Tab><Tab>=<Tab><Tab>add_cnt2 && cnt2 == ;
:ab Cnt0 iid0d$ireg [ : 0] cnt0 ;<Enter>wire add_cnt0 ;<Enter>wire end_cnt0 ;<Enter>//cnt0<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt0 <= 0;<Enter>end<Enter>else if(add_cnt0)begin<Enter>if(end_cnt0)<Enter>cnt0 <= 0;<Enter>else<Enter>cnt0 <= cnt0 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt0<Tab><Tab>=<Tab><Tab>; <Enter>assign end_cnt0<Tab><Tab>=<Tab><Tab>add_cnt0 && cnt0 == ;
:ab Cnt1 iid0d$ireg [ : 0] cnt1 ;<Enter>wire add_cnt1 ;<Enter>wire end_cnt1 ;<Enter>//cnt1<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt1 <= 0;<Enter>end<Enter>else if(add_cnt1)begin<Enter>if(end_cnt1)<Enter>cnt1 <= 0;<Enter>else<Enter>cnt1 <= cnt1 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt1<Tab><Tab>=<Tab><Tab>; <Enter>assign end_cnt1<Tab><Tab>=<Tab><Tab>add_cnt1 && cnt1 == ;
:ab Cnt2 iid0d$ireg [ : 0] cnt2 ;<Enter>wire add_cnt2 ;<Enter>wire end_cnt2 ;<Enter>//cnt2<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt2 <= 0;<Enter>end<Enter>else if(add_cnt2)begin<Enter>if(end_cnt2)<Enter>cnt2 <= 0;<Enter>else<Enter>cnt2 <= cnt2 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt2<Tab><Tab>=<Tab><Tab>; <Enter>assign end_cnt2<Tab><Tab>=<Tab><Tab>add_cnt2 && cnt2 == ;
:ab Cnt3 iid0d$ireg [ : 0] cnt3 ;<Enter>wire add_cnt3 ;<Enter>wire end_cnt3 ;<Enter>//cnt3<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt3 <= 0;<Enter>end<Enter>else if(add_cnt3)begin<Enter>if(end_cnt3)<Enter>cnt3 <= 0;<Enter>else<Enter>cnt3 <= cnt3 + 1;<Enter>end<Enter>end<Enter><Enter>assign add_cnt3<Tab><Tab>=<Tab><Tab>; <Enter>assign end_cnt3<Tab><Tab>=<Tab><Tab>add_cnt3 && cnt3 == ;
"-----------------------------------------------------------------------状态机-----------------------------------------------------------------"
:ab Ztj4 always@(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>state_c <= IDLE;<Enter>end<Enter>else begin<Enter>state_c <= state_n;<Enter>end<Enter>end<Enter><Enter><Enter>always@(*)begin<Enter>case(state_c)<Enter>IDLE:begin<Enter>if(idl2s1_start)begin<Enter>state_n = S1;<Enter>end<Enter>else begin<Enter>state_n = state_c;<Enter>end<Enter>end<Enter>S1:begin<Enter>if(s12s2_start)begin<Enter>state_n = S2;<Enter>end<Enter>else begin<Enter>state_n = state_c;<Enter>end<Enter>end<Enter>S2:begin<Enter>if(s22s3_start)begin<Enter>state_n = S3;<Enter>end<Enter>else begin<Enter>state_n = state_c;<Enter>end<Enter>end<Enter>default:begin<Enter>state_n = IDLE;<Enter>end<Enter>endcase<Enter>end<Enter><Enter>assign idl2s1_start<Tab><Tab>=<Tab><Tab>state_c==IDLE && ;<Enter>assign s12s2_start<Tab><Tab>=<Tab><Tab>state_c==S1 && ;<Enter>assign s22s3_start<Tab><Tab>=<Tab><Tab>state_c==S2 && ;<Enter><Enter><Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>out1 <=1'b0; <Enter>end<Enter>else if(state_c==S1)begin<Enter>out1 <= 1'b1;<Enter>end<Enter>else begin<Enter>out1 <= 1'b0;<Enter>end<Enter>end
:ab Ztj //state_c<enter>always@(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>state_c <= IDLE;<Enter>end<Enter>else begin<Enter>state_c <= state_n;<Enter>end<Enter>end<Enter><Enter>//state_n<enter>always@(*)begin<Enter>case(state_c)<Enter>IDLE:begin<Enter>if()begin<Enter>state_n = S1;<Enter>end<Enter>else begin<Enter>state_n = state_c;<Enter>end<Enter>end<Enter>S1:begin<Enter>if()begin<Enter>state_n = S2;<Enter>end<Enter>else begin<Enter>state_n = state_c;<Enter>end<Enter>end<Enter>S2:begin<Enter>if()begin<Enter>state_n = S3;<Enter>end<Enter>else begin<Enter>state_n = state_c;<Enter>end<Enter>end<Enter>default:begin<Enter>state_n = IDLE;<Enter>end<Enter>endcase<Enter>end<Enter><Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>out1 <=1'b0; <Enter>end<Enter>else if(state_c==S1)begin<Enter>out1 <= 1'b1;<Enter>end<Enter>else begin<Enter>out1 <= 1'b0;<Enter>end<Enter>end
"---------------------------------input对齐规则-----------------------------------------"
:ab input48 input [47: 0] <ESC>032ldwi
:ab input32 input [31: 0] <ESC>032ldwi
:ab input31 input [30: 0] <ESC>032ldwi
:ab input30 input [29: 0] <ESC>032ldwi
:ab input29 input [28: 0] <ESC>032ldwi
:ab input28 input [27: 0] <ESC>032ldwi
:ab input27 input [26: 0] <ESC>032ldwi
:ab input26 input [25: 0] <ESC>032ldwi
:ab input25 input [24: 0] <ESC>032ldwi
:ab input24 input [23: 0] <ESC>032ldwi
:ab input23 input [22: 0] <ESC>032ldwi
:ab input22 input [21: 0] <ESC>032ldwi
:ab input21 input [20: 0] <ESC>032ldwi
:ab input20 input [19: 0] <ESC>032ldwi
:ab input19 input [18: 0] <ESC>032ldwi
:ab input18 input [17: 0] <ESC>032ldwi
:ab input17 input [16: 0] <ESC>032ldwi
:ab input16 input [15: 0] <ESC>032ldwi
:ab input15 input [14: 0] <ESC>032ldwi
:ab input14 input [13: 0] <ESC>032ldwi
:ab input13 input [12: 0] <ESC>032ldwi
:ab input12 input [11: 0] <ESC>032ldwi
:ab input11 input [10: 0] <ESC>032ldwi
:ab input10 input [ 9: 0] <ESC>032ldwi
:ab input9 input [ 8: 0] <ESC>032ldwi
:ab input8 input [ 7: 0] <ESC>032ldwi
:ab input7 input [ 6: 0] <ESC>032ldwi
:ab input6 input [ 5: 0] <ESC>032ldwi
:ab input5 input [ 4: 0] <ESC>032ldwi
:ab input4 input [ 3: 0] <ESC>032ldwi
:ab input3 input [ 2: 0] <ESC>032ldwi
:ab input2 input [ 1: 0] <ESC>032ldwi
:ab input input <ESC>032ldwi
"---------------------------------output对齐规则-----------------------------------2---"
:ab outputreg48 output reg [47: 0] <ESC>032ldwi
:ab outputreg32 output reg [31: 0] <ESC>032ldwi
:ab outputreg31 output reg [30: 0] <ESC>032ldwi
:ab outputreg30 output reg [29: 0] <ESC>032ldwi
:ab outputreg29 output reg [28: 0] <ESC>032ldwi
:ab outputreg28 output reg [27: 0] <ESC>032ldwi
:ab outputreg27 output reg [26: 0] <ESC>032ldwi
:ab outputreg26 output reg [25: 0] <ESC>032ldwi
:ab outputreg25 output reg [24: 0] <ESC>032ldwi
:ab outputreg24 output reg [23: 0] <ESC>032ldwi
:ab outputreg23 output reg [22: 0] <ESC>032ldwi
:ab outputreg22 output reg [21: 0] <ESC>032ldwi
:ab outputreg21 output reg [20: 0] <ESC>032ldwi
:ab outputreg20 output reg [19: 0] <ESC>032ldwi
:ab outputreg19 output reg [18: 0] <ESC>032ldwi
:ab outputreg18 output reg [17: 0] <ESC>032ldwi
:ab outputreg17 output reg [16: 0] <ESC>032ldwi
:ab outputreg16 output reg [15: 0] <ESC>032ldwi
:ab outputreg15 output reg [14: 0] <ESC>032ldwi
:ab outputreg14 output reg [13: 0] <ESC>032ldwi
:ab outputreg13 output reg [12: 0] <ESC>032ldwi
:ab outputreg12 output reg [11: 0] <ESC>032ldwi
:ab outputreg11 output reg [10: 0] <ESC>032ldwi
:ab outputreg10 output reg [ 9: 0] <ESC>032ldwi
:ab outputreg9 output reg [ 8: 0] <ESC>032ldwi
:ab outputreg8 output reg [ 7: 0] <ESC>032ldwi
:ab outputreg7 output reg [ 6: 0] <ESC>032ldwi
:ab outputreg6 output reg [ 5: 0] <ESC>032ldwi
:ab outputreg5 output reg [ 4: 0] <ESC>032ldwi
:ab outputreg4 output reg [ 3: 0] <ESC>032ldwi
:ab outputreg3 output reg [ 2: 0] <ESC>032ldwi
:ab outputreg2 output reg [ 1: 0] <ESC>032ldwi
:ab outputreg output reg <ESC>032ldwi
:ab output48 output wire [47: 0] <ESC>032ldwi
:ab output32 output wire [31: 0] <ESC>032ldwi
:ab output31 output wire [30: 0] <ESC>032ldwi
:ab output30 output wire [29: 0] <ESC>032ldwi
:ab output29 output wire [28: 0] <ESC>032ldwi
:ab output28 output wire [27: 0] <ESC>032ldwi
:ab output27 output wire [26: 0] <ESC>032ldwi
:ab output26 output wire [25: 0] <ESC>032ldwi
:ab output25 output wire [24: 0] <ESC>032ldwi
:ab output24 output wire [23: 0] <ESC>032ldwi
:ab output23 output wire [22: 0] <ESC>032ldwi
:ab output22 output wire [21: 0] <ESC>032ldwi
:ab output21 output wire [20: 0] <ESC>032ldwi
:ab output20 output wire [19: 0] <ESC>032ldwi
:ab output19 output wire [18: 0] <ESC>032ldwi
:ab output18 output wire [17: 0] <ESC>032ldwi
:ab output17 output wire [16: 0] <ESC>032ldwi
:ab output16 output wire [15: 0] <ESC>032ldwi
:ab output15 output wire [14: 0] <ESC>032ldwi
:ab output14 output wire [13: 0] <ESC>032ldwi
:ab output13 output wire [12: 0] <ESC>032ldwi
:ab output12 output wire [11: 0] <ESC>032ldwi
:ab output11 output wire [10: 0] <ESC>032ldwi
:ab output10 output wire [ 9: 0] <ESC>032ldwi
:ab output9 output wire [ 8: 0] <ESC>032ldwi
:ab output8 output wire [ 7: 0] <ESC>032ldwi
:ab output7 output wire [ 6: 0] <ESC>032ldwi
:ab output6 output wire [ 5: 0] <ESC>032ldwi
:ab output5 output wire [ 4: 0] <ESC>032ldwi
:ab output4 output wire [ 3: 0] <ESC>032ldwi
:ab output3 output wire [ 2: 0] <ESC>032ldwi
:ab output2 output wire [ 1: 0] <ESC>032ldwi
:ab output output wire <ESC>032ldwi
"---------------------------------wire对齐规则-------------------------------------2---"
:ab wire48 wire [47: 0] <ESC>032ldwi
:ab wire32 wire [31: 0] <ESC>032ldwi
:ab wire31 wire [30: 0] <ESC>032ldwi
:ab wire30 wire [29: 0] <ESC>032ldwi
:ab wire29 wire [28: 0] <ESC>032ldwi
:ab wire28 wire [27: 0] <ESC>032ldwi
:ab wire27 wire [26: 0] <ESC>032ldwi
:ab wire26 wire [25: 0] <ESC>032ldwi
:ab wire25 wire [24: 0] <ESC>032ldwi
:ab wire24 wire [23: 0] <ESC>032ldwi
:ab wire23 wire [22: 0] <ESC>032ldwi
:ab wire22 wire [21: 0] <ESC>032ldwi
:ab wire21 wire [20: 0] <ESC>032ldwi
:ab wire20 wire [19: 0] <ESC>032ldwi
:ab wire19 wire [18: 0] <ESC>032ldwi
:ab wire18 wire [17: 0] <ESC>032ldwi
:ab wire17 wire [16: 0] <ESC>032ldwi
:ab wire16 wire [15: 0] <ESC>032ldwi
:ab wire15 wire [14: 0] <ESC>032ldwi
:ab wire14 wire [13: 0] <ESC>032ldwi
:ab wire13 wire [12: 0] <ESC>032ldwi
:ab wire12 wire [11: 0] <ESC>032ldwi
:ab wire11 wire [10: 0] <ESC>032ldwi
:ab wire10 wire [ 9: 0] <ESC>032ldwi
:ab wire9 wire [ 8: 0] <ESC>032ldwi
:ab wire8 wire [ 7: 0] <ESC>032ldwi
:ab wire7 wire [ 6: 0] <ESC>032ldwi
:ab wire6 wire [ 5: 0] <ESC>032ldwi
:ab wire5 wire [ 4: 0] <ESC>032ldwi
:ab wire4 wire [ 3: 0] <ESC>032ldwi
:ab wire3 wire [ 2: 0] <ESC>032ldwi
:ab wire2 wire [ 1: 0] <ESC>032ldwi
:ab wire1 wire <ESC>032ldwi
"----------------------------------reg对齐规则-------------------------------------2---"
:ab reg48 reg [47: 0] <ESC>032ldwi
:ab reg32 reg [31: 0] <ESC>032ldwi
:ab reg31 reg [30: 0] <ESC>032ldwi
:ab reg30 reg [29: 0] <ESC>032ldwi
:ab reg29 reg [28: 0] <ESC>032ldwi
:ab reg28 reg [27: 0] <ESC>032ldwi
:ab reg27 reg [26: 0] <ESC>032ldwi
:ab reg26 reg [25: 0] <ESC>032ldwi
:ab reg25 reg [24: 0] <ESC>032ldwi
:ab reg24 reg [23: 0] <ESC>032ldwi
:ab reg23 reg [22: 0] <ESC>032ldwi
:ab reg22 reg [21: 0] <ESC>032ldwi
:ab reg21 reg [20: 0] <ESC>032ldwi
:ab reg20 reg [19: 0] <ESC>032ldwi
:ab reg19 reg [18: 0] <ESC>032ldwi
:ab reg18 reg [17: 0] <ESC>032ldwi
:ab reg17 reg [16: 0] <ESC>032ldwi
:ab reg16 reg [15: 0] <ESC>032ldwi
:ab reg15 reg [14: 0] <ESC>032ldwi
:ab reg14 reg [13: 0] <ESC>032ldwi
:ab reg13 reg [12: 0] <ESC>032ldwi
:ab reg12 reg [11: 0] <ESC>032ldwi
:ab reg11 reg [10: 0] <ESC>032ldwi
:ab reg10 reg [ 9: 0] <ESC>032ldwi
:ab reg9 reg [ 8: 0] <ESC>032ldwi
:ab reg8 reg [ 7: 0] <ESC>032ldwi
:ab reg7 reg [ 6: 0] <ESC>032ldwi
:ab reg6 reg [ 5: 0] <ESC>032ldwi
:ab reg5 reg [ 4: 0] <ESC>032ldwi
:ab reg4 reg [ 3: 0] <ESC>032ldwi
:ab reg3 reg [ 2: 0] <ESC>032ldwi
:ab reg2 reg [ 1: 0] <ESC>032ldwi
:ab reg1 reg <ESC>032ldwi
"---------------------------------文件头注释规则---------------------------------------"
:imap <F2> <ESC>ms:call AddAuthor()<cr>
:map <F2> ms:call AddAuthor()<cr>
function AddAuthor()
let n=1
while n < 6
let line = getline(n)
if line=~'[#]*\s*\*\s*\S*Last\s*modified\s*:\s*\S*.*$'
call UpdateTitle()
return
endif
let n = n + 1
endwhile
if &filetype == 'sh'
call AddTitleForShell()
elseif &filetype == 'python'
call AddTitleForPython()
else
call AddTitleForC()
endif
endfunction
function UpdateTitle()
normal m'
execute '/* Last Modified\s*:/s@:.*$@\=strftime(": %Y-%m-%d %H:%M")@'
normal mk
execute '/* Filename\s*:/s@:.*$@\=": ".expand("%:t")@'
execute "noh"
normal 'k
echohl WarningMsg | echo "Successful in updating the copy right." |echohl None
endfunction
function AddTitleForC()
call append(0,"// *********************************************************************")
call append(1,"// File Name : ".expand("%:t"))
call append(2,"// Author : YYB")
call append(3,"// Create Date : ".strftime("%Y-%m-%d %H:%M"))
call append(4,"// Last Modified : ".strftime("%Y-%m-%d %H:%M"))
call append(5,"// Description : ")
call append(6,"// Notes : ")
call append(7,"// *********************************************************************")
echohl WarningMsg | echo "Successful in adding the copyright." | echohl None
endfunction
"" add comment for Python
function AddTitleForPython()
call append(0,"#!/usr/bin/python")
call append(1,"# -*- coding: UTF-8 -*-")
call append(2,"")
call append(3,"# ***********************************************************************")
call append(4,"# File Name : ".expand("%:t"))
call append(5,"# Author : YYB")
call append(6,"# Create Date : ".strftime("%Y-%m-%d %H:%M"))
call append(7,"# Last Modified : ".strftime("%Y-%m-%d %H:%M"))
call append(8,"# Description : ")
call append(9,"# Notes : ")
call append(10,"# ***********************************************************************")
echohl WarningMsg | echo "Successful in adding the copyright." | echohl None
endfunction
"" add conment for shell
function AddTitleForShell()
call append(0,"#!/bin/bash")
call append(1,"# ***********************************************************************")
call append(2,"# File Name : ".expand("%:t"))
call append(3,"# Author : YYB")
call append(4,"# Create Date : ".strftime("%Y-%m-%d %H:%M"))
call append(5,"# Last Modified : ".strftime("%Y-%m-%d %H:%M"))
call append(6,"# Description : ")
call append(7,"# Notes : ")
call append(8,"# ***********************************************************************")
endfunction
"---------------------------------------各插件配置-------------------------------------------"
":ab // <Esc>0i// ii
:imap <F1> <ESC>:NERDTree<cr><cr>
:map <F1> :NERDTree<cr><cr>
let g:miniBufExplMapCTabSwitchBufs = 1
let g:miniBufExplMapWindowNavVim = 1
:map <F9> :TMiniBufExplorer<cr>
:imap <F9> <ESC>:TMiniBufExplorer<cr>
:ab cmb <ESC>:CMiniBufExplorer
:map <S-j> <C-j>
:map <S-k> <C-k>
:map <S-h> <C-h>
:map <S-l> <C-l>
"语言设置f
set encoding=utf-8
set termencoding=utf-8
set fileencoding=chinese
set fileencodings=ucs-bom,utf-8,chinese
set langmenu=zh_CN.utf-8
source $VIMRUNTIME/delmenu.vim
source $VIMRUNTIME/menu.vim
language messages zh_cn.utf-8
set tags=tags;
set autochdir
"NERDTree配置
map <F1> :NERDTreeToggle<CR>
map <C-F1> :NERDTreeFind<CR>
let NERDTreeChDirMode=2 "选中root即设置为当前目录
let NERDTreeQuitOnOpen=1 "打开文件时关闭树
let NERDTreeShowBookmarks=1 "显示书签
let NERDTreeMinimalUI=1 "不显示帮助面板
let NERDTreeDirArrows=1 "目录箭头 1 显示箭头 0传统+-|号
:set guioptions-=m "remove menu bar
:set guioptions-=T "remove toolbar
:set guioptions-=r "remove right-hand scroll bar
:set guioptions-=L "remove left-hand scroll bar</span>
:set showmatch
:set matchtime=2
set guifont=新宋体:h16:cGB2312
"自动补全
":inoremap ( ()<ESC>i
":inoremap ) <c-r>=ClosePair(')')<CR>
"":inoremap { {<CR>}<ESC>O
"":inoremap } <c-r>=ClosePair('}')<CR>
":inoremap [ []<ESC>i
":inoremap ] <c-r>=ClosePair(']')<CR>
":inoremap " ""<ESC>i
"function! ClosePair(char)
" if getline('.')[col('.') - 1] == a:char
" return "\<Right>"
" else
" return a:char
" endif
"endfunction
filetype plugin indent on
:ab Initial initial begin<Enter>#1;<Enter>end
set diffexpr=MyDiff()
function MyDiff()
let opt = '-a --binary '
if &diffopt =~ 'icase' | let opt = opt . '-i ' | endif
if &diffopt =~ 'iwhite' | let opt = opt . '-b ' | endif
let arg1 = v:fname_in
if arg1 =~ ' ' | let arg1 = '"' . arg1 . '"' | endif
let arg2 = v:fname_new
if arg2 =~ ' ' | let arg2 = '"' . arg2 . '"' | endif
let arg3 = v:fname_out
if arg3 =~ ' ' | let arg3 = '"' . arg3 . '"' | endif
let eq = ''
if $VIMRUNTIME =~ ' '
if &sh =~ '\<cmd'
let cmd = '""' . $VIMRUNTIME . '\diff"'
let eq = '"'
else
let cmd = substitute($VIMRUNTIME, ' ', '" ', '') . '\diff"'
endif
else
let cmd = $VIMRUNTIME . '\diff'
endif
silent execute '!' . cmd . ' ' . opt . arg1 . ' ' . arg2 . ' > ' . arg3 . eq
endfunction
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