【VHDL】八三編碼器

八三編碼器

**方法一：**使用IF語句程序：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ENCODER IS
PORT( IN1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	 OUT1: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END;

ARCHITECTURE ONE OF ENCODER IS
BEGIN
PROCESS(IN1)
BEGIN

	if IN1(7)='1' THEN OUT1<="111";
	ELSIF IN1(6)='1' THEN OUT1<="110";
	ELSIF IN1(5)='1' THEN OUT1<="101";
	ELSIF IN1(4)='1' THEN OUT1<="100";
	ELSIF IN1(3)='1' THEN OUT1<="011";
	ELSIF IN1(2)='1' THEN OUT1<="010";
	ELSIF IN1(1)='1' THEN OUT1<="001";
	ELSIF IN1(0)='1' THEN OUT1<="000";
	ELSE OUT1<="XXX";
END IF;
END PROCESS;
end;

先寫個一。