【VHDL】四位全減器

全減器真值表理解：點擊瞭解

採用元件例化方式，選擇頂層文件

一位半減器程序：

library ieee;
use ieee.std_logic_1164.all;

entity bjq is
port (x_h,y_h:in std_logic;
c1,s1:out std_logic);
end;

architecture one of bjq is
begin
process(x_h,y_h)
begin
s1<= x_h xor y_h;
c1<= (not x_h) and y_h;
end process;
end; 

或門程序：

library ieee;
use ieee.std_logic_1164.all;

entity org is
port(a,b:in std_logic;
		o:out std_logic);
end entity;

architecture one of org is
begin
o<=a or b;
end;

一位全減器程序：

library ieee;
use ieee.std_logic_1164.all;

entity qjq is
port (x,y,c0:in std_logic;
	c_out,s_out:out std_logic);
end;

architecture one of qjq is
component bjq
port (x_h,y_h:in std_logic;
c1,s1:out std_logic);
end component;

component org
port(a,b:in std_logic;
		o:out std_logic);
end component;

signal d,e,f:std_logic;
begin
u1:bjq port map(x_h=>x,y_h=>y,c1=>e,s1=>d);
u2:bjq port map(x_h=>e,y_h=>c0,c1=>f,s1=>s_out);
u3:org port map(a=>e,b=>f,o=>c_out);
end;

四位全減器程序：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity siwei is
port(A,B: in std_logic_vector(3 downto 0);
	  C0: in std_logic; 
	  S:out std_logic_vector(3 downto 0);
	  C1: out std_logic );
end siwei;

architecture full of siwei is

component qjq
port(x,y,c0:in std_logic;
	c_out,s_out:out std_logic);
end component;

signal q1,q2,q3: std_logic;
begin
u1:qjq port MAP(x=>A(0),y=>B(0),c0=>C0,c_out=>q1,s_out=>S(0)); 
u2:qjq port MAP(x=>A(1),y=>B(1),c0=>q1,c_out=>q2,s_out=>S(1));
u3:qjq port MAP(x=>A(2),y=>B(2),c0=>q2,c_out=>q3,s_out=>S(2));
u4:qjq port MAP(x=>A(3),y=>B(3),c0=>q3,c_out=>C1,s_out=>S(3));
end;