【VHDL】隨機存儲器RAM、只讀存儲器ROM

【VHDL】隨機存儲器設置

RAM程序：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY RAM_8 IS
PORT(CS,RD,WR:IN STD_LOGIC;
		CLK:IN STD_LOGIC;
		ADDR:IN INTEGER RANGE 0 TO 15;
		DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
END ENTITY;

ARCHITECTURE ONE OF RAM_8 IS
	TYPE MEMORY IS ARRAY(15 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);				--zi ding yi yigeshujuleixing
	SIGNAL RAM:MEMORY;
BEGIN
	WRT:PROCESS(CS,WR,RD,CLK,DIN)
	   BEGIN
		IF(CS='0' AND WR='1' AND RD='0') THEN
			IF CLK' EVENT AND CLK='1' THEN
				RAM(ADDR)<=DIN;  --FAN JIAN HAO BE XIE ROU SHUJU
			END IF;
		END IF;
	   END PROCESS;
	RAD:PROCESS(CS,WR,RD,CLK)
		BEGIN
		IF(CS='0' AND WR='0' AND RD='1') THEN
			IF CLK' EVENT AND CLK='1' THEN
				DOUT<=RAM(ADDR);  --ZHE GE DIZHI XIA DE SHUSONG CHUQU
			END IF;
		ELSE DOUT <=(OTHERS=>'Z');  --ROUGUO WUXIAO BAOCHI GAOZUTAI
		END IF;
	   END PROCESS;
END;

ROM程序：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ROM_8 IS
PORT(EN:IN STD_LOGIC;
	ADRSS:IN INTEGER RANGE 0 TO 7;
	Q_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;

ARCHITECTURE ONE OF ROM_8 IS
BEGIN
	PROCESS(EN)
	BEGIN
		IF EN='0' THEN Q_OUT<=(OTHERS=>'Z');
		ELSIF EN='1' THEN 
			CASE ADRSS IS
			WHEN 0 =>Q_OUT<="01110000";
			WHEN 1 =>Q_OUT<="01110001";
			WHEN 2 =>Q_OUT<="01110010";
			WHEN 3 =>Q_OUT<="01110100";
			WHEN 4 =>Q_OUT<="01111000";
			WHEN 5 =>Q_OUT<="01111100";
			WHEN 6 =>Q_OUT<="01111110";
			WHEN 7 =>Q_OUT<="01111111";
			END CASE;
		ELSE NULL;
	END IF;
	END PROCESS;
	
END;