module dead_time(
input wire clk,
input wire rst_n
);
wire PWM_Source;
reg w_PWM_Source;
reg pwm_a_dly;
reg pwm_a_dly1;
wire o_square_wave_0;
reg o_square_wave_1;
reg [16:0]w_time_cnt;
reg [16:0]w_cnt;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
w_cnt <= 'b0;
else if(w_cnt == 99)
w_cnt <= 0;
else
w_cnt <= w_cnt+1;
end
always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0)
w_PWM_Source <= 'b0;
else if(w_cnt == 49)
w_PWM_Source <= ~w_PWM_Source;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
o_square_wave_1 <= 'b0;
else if(w_time_cnt == 11'd19)
o_square_wave_1 <= pwm_a_dly1;
end
assign PWM_Source = w_PWM_Source ;
////dead time
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
pwm_a_dly <= 'd0;
pwm_a_dly1<= 'd0;
end
else
begin
pwm_a_dly <= PWM_Source;
pwm_a_dly1<= pwm_a_dly;
end
end
assign o_square_wave_0 = pwm_a_dly1;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
w_time_cnt <= 'd0;
else if(pwm_a_dly1 != pwm_a_dly)
w_time_cnt <= 'd0;
else if(w_time_cnt == 11'd20)
w_time_cnt <= 11'd20;
else
w_time_cnt <= w_time_cnt + 1'b1;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
o_square_wave_1 <= 'b0;
else if(w_time_cnt == 11'd19)
o_square_wave_1 <= pwm_a_dly1;
end
endmodule