FPGA 關於錯誤（10200）

本人在調試FPGA時有時會出現以下錯誤：

Error (10200): Verilog HDL Conditional Statement error at delay.v(23): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

問題原因在於筆者用了以下語句
always@(posedge clk or negedge rst_n)
卻粗心的忘了對rst_n進行判斷了寫成如下語句了

always@(posedge clk or negedge rst_n)
begin 
 if(txd_flag)
    if(state < 4'd9)
           state<=state+1;
    else
          state<=0;
 else 
            state<=state;
end

而正確的應該是

always@(posedge clk or negedge rst_n)
begin 
 if(!rst_n)
        begin
            state<=0;
        end
 else if(txd_flag)
    if(state < 4'd9)
           state<=state+1;
    else
          state<=0;
 else 
            state<=state;
end